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ref-sdr-sdram-verilog
- sdram控制器的开发程序，还有文档，可以参考以下
ref-sdr-sdram-vhdl
- 标准SDR SDRAM控制器参考设计_verilog_lattice\\sdr_ctrl.v
USB and SDRAM Controller
- 基于CY7C68013A的Slave FIFO和SDRAM控制器
基于SDRAM的图像存储器
- 基于FPGA的SDRAM控制器设计 摘 要：介绍了SDRAM的特点和工作原理，提出了一种基于FPGA的SDRAM控制器设计方法，采用Verilog语言完成的控制器的设计，可以很方便地对SDRAM进行操作。控制器在大容量数据记录仪扩展缓存得到了很好的应用。
verilog 128位 突发4. sdr fpga控制器
- verilog 128位 突发4. sdr fpga控制器,verilog 128 bit unexpected 4. sdr fpga controller
sdram_vhdl_lattice.rar
- lattice sdram 控制器VHDL源代码,Sound code of Lattice Sdram Controller based on VHDL
SDRAM_VerilogCode.rar
- 基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。,FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
sdram_ver_134
- SDRAM控制器的源代码打包下载，不错不错值得-SDRAM controller source code pack download, well worth a good try
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
Sdram_Control_4Port
- SDRAM控制器HDL实现，sdram为美光公司的-sdram controller
SDRAM_CONTROLlER_Modelsim
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和文档-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
sdram_vhd_134
- Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
newSD
- 基于Verilog的完整SDRAM控制器时序代码-Based on a complete Verilog timing SDRAM controller code
VerilogfoFPGAbasedSDRAMController
- 使用Verilog实现基于FPGA的SDRAM控制器-The use of Verilog for FPGA-based SDRAM Controller
hssdrc_latest
- SDRAM 控制器 Verilog实现，很有借鉴意义。-SDRAM controller core Verilog implementation。With good referential significance.
module
- SDRAM控制器源代码，已经过调试，可以试用一下。-SDRAM controller source code, has been testing, you can try.
SDRAMcontrollor
- SDRAM控制器，以下是我用VHDL编写SDRAM Controller的全部资料。文档提供的SDRAM控制器能工作在125MHz，我在实际工程中用到了120MHz，但没有再往上做测试了-SDRAM controller, the following is my SDRAM Controller using VHDL to prepare all the information. Documentation provided by SDRAM controller can work in the
ddr_verilog_xilinx
- xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
FPGAbasedSDRAMControll
- 基于FPGA的SDRAM控制器 Realization FPGA-based SDRAM Controller with Verilog-FPGA-based SDRAM Controller Realization FPGA-based SDRAM Controller with Verilog