搜索资源列表
led3
- lcd interface in spartan3e code with verilog domine
sp3e_fifo
- xilinx spartan3e fifo读写测试工程 仿真通过。全套工程。-xilinx spartan3e fifo read and write test engineering simulation through.
digitalclock_demo
- 该程序适用于xilinx公司的FPGA开发板，spartan3E系列250型号 通过verilog编程实现数字钟的功能，下板子验证可用！-This procedure applies to xilinx FPGA development board Series 250 Model spartan3E digital clock verilog programming under the board to verify available!
VHDL_uart
- 用xilinx的FPGA-spartan3E实现uart，固定波特率9600，偶校验，系统时钟50MHz，能够实现将从串口调试助手发送到FPGA的数据重新发回串口调试助手-using xilinx s FPGA-spartan3E to implement uart with a baudrate of 9600, even parity check. The system frequency is 50MHz.It can turn the data from serial assistant
Xilinx_Spartan3E_VGA_PS2
- 使用Spartan3E 开发板实现VGA显示和PS2键盘接口，完成了简单的文字处理功能和图片显示功能。-Use Spartan3E development board to achieve VGA display and PS2 keyboard interface, complete a simple word processing features and picture display.
UniversalDIV
- UNIVERSAL FREQUENCY DIVIDER pin sets for Digilent Basys 2 (Spartan3E-250) fout = (K(0)*100+ K(1)*10 + K(2))*10K(3)
prog_seq_FIN
- Verilog Programmable Sequence Detector on Spartan3E
Counter_Debounce
- Verilog 3-bit Inc/Dec Counter on Spartan3E
Lab_02
- Verilog 3-to-8 Decoder on Spartan3E. Use 3 switches (SW[2:0]) as inputs. Keep SW[2] as MSB. Use 8 LEDs (LD[7:0]) as decoded outputs. i.e. if all input switches are turned off, LD0 should light up.
vga_vhdl
- vga vhdl 语言编写的vga驱动代码在spartan3e开发板上通过-vga vhdl language vga driver code development board through the spartan3e
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
ADPLL
- This paper presents the ADPLL design using Verilog and its implementation on FPGA. ADPLL is designed using Verilog HDL. Xilinx ISE 12.1 Simulator is used for simulating Verilog Code. This paper gives details of the basic blocks of an ADPLL. In this p
LCD_counter
- xilinx spartan3E 开发板上LCD显示屏驱动，并显示周期为一分钟的计数器。-Xilinx spartan3E development board on the LCD display drive, and display the cycle counter for a minute.
rotation_adjust
- xilinx spartan3E开发板上旋转按钮的驱动，利用旋钮旋转控制LED灯的亮暗程度，从灭到亮有10种不同的亮度。-Xilinx spartan3E development board rotate button on the drive, using the knob control LED lamp brightness level, there are 10 kinds of different from out to bright brightness.
VGA1
- 这是我自己的一个流水灯的设计编程 在ise10.1环境下做的Verilog编程 用Spartan3E basys2开发板可以实现八个led灯的循环 有一个复位rst 设计关键是分频器的设计 这里运用的是d触发器实现50MHz的50M分频-This is my own design of a light water program in ise10.1 do Verilog programming environment with Spartan3E basys2 development bo
spwm_wave
- 此程序为在spartan3e上经过验证的可以运行的通过查表法产生的spwm发生器-the project can produce spwm wave
udpSender
- Module Ethernet UDPsender for spartan3E.
vga_controller
- vga controller (640x480) Spartan3E FPGA board
FPGA_LED_testcode
- LED test on Spartan3E , speed variation, light intensity variation
sdram
- ISE14.4环境编程，XILINX spartan3E,SDRAM完整编程-xilinx sdram