搜索资源列表
niossram
- altera fpga ep3c25器件微处理器开发，niosii+sram, 已编译通过，可直接下载到开发板-altera fpga ep3c25 the development of microprocessor devices, niosii+ sram, compiled through, can be directly downloaded to the development board
AVR
- avrC语言 全局和局部变量 • 全局变量 – 在 startup 初始化 – 存储于 SRAM – 必须加载到寄存器堆中 • 局部变量 – 在函数初期初始化 – 存储于寄存器当中直至函数结束-awqvrCyuyan] 全局和局部变量 • 全局变量 – 在 startup 初始化 – 存储于 SRAM – 必须加载到寄存器堆中 • 局部变量 – 在函数初期初始化 – 存储于寄存器当中直至函
FGPA-SRAM-Programe
- FPGA编程方法介绍，方便学习VHDL,公供大家参考-fpga programe medoth, study hardware vhdl language
sram216
- SRAM IS61LVC12824,读写控制程序，用CPLD 95216设计-SRAM IS61LVC12824, read and write control procedures, with the design of CPLD 95216
use_SRAM_design_FIFO.pdf
- 利用sram技术设计的一个FIFO-failed to translate
interleaver
- This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Protecting_FPGA
- How to protect your FPGA design (IP) on SRAM based FPGA s against copying.
PWM
- verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
SRAM_with_con
- 带有控制器的SRAM，提供一个地址选通脉冲ADS，一个读/写信号R_W,一个时钟信号和复位信号，包含了测试文件。-Controller with the SRAM, providing a strobe pulse Address ADS, a read/write signal R_W, a clock signal and reset signal, including the test documents.
de2_lcm_ccd_sram
- 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
SRAM_Controller
- Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
SRAM_2006
- PPT of the SRAM, new development
IS61WV51216
- iss simulation model for 512KX16 SRAM
sram_test
- fpga读写SRAM的VERILOG 代码-the verilog code of fpga write/read sram
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
SSRAM_CONTROLLER
- sram controller design for GSI sram working
code_20-08-09
- CPLD Interface code with SRAM
FPGA2SRAM
- 利用FPGA向SRAM中传输数据，可用于FPGA芯片的初始化和配置-The use of FPGA to transmit data to the SRAM, FPGA chips can be used for initialization and configuration
512
- several examples in Sram access in Spatan 3E
rams
- several examples of accessing SRAM in Spartan3