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frequency-divider
- 用VERILOG 语言写的数控分频器,可能输入时钟信号实现任意整数倍的分频,-NC divider, with the words written in VERILOG HDL, can achieve any integer multiple of the input clock frequency, contains the entire project file.
myproj
- 1) 可以产生四种波形:正弦波,方波,三角波,锯齿波。 2) 实现分频可调,分频比从2~256可调,通过两个按键进行+1和-1的调整。 3) 信号幅度可调,幅度增益从1~4倍可调,过两个按键进行+1和-1的调整。 4) 8位数码管的前3位显示分频比,最后一位显示幅度增益,中间的四位分别代表四种波形是否输出,若输出则显示’1’,否则显示’0’。 5) 可实现四种波形的叠加,当有两种波形叠加时,增益不能超过3,当是四种或三种波形叠加时,增益只能为1. -1) can produc
ex1_clkdiv
- Verilog语言编写,通过此代码控制CPLD输出任意偶数倍分频-Verilog language, through this code control CPLD any even multiple output divider
UTP_channel_response_generate
- 该段代码生成不同长度下,双绞线信道的远端衰减冲激响应系数。双绞线频域带宽最高可达106MHz,采样率设置时必须大于两倍的频域带宽。双绞线信道模型使用ITU-T-SG15 contribution 11GS3-029中的模型。-This code generates a different length, the distal twisted channel impulse response attenuation coefficient. Twisted frequency domain ban
freq_div
- //奇数倍分频器基于verilog HDL.-(ODD number)Freq Divider based on Verilog HDL.
kbfp
- 实现任意整数倍的信号分频,可调,不存在毛刺,波形完整,可运于信号的分析与检测-Arbitrary integer multiple of the signal frequency, adjustable, there is no glitch, waveform integrity, and can transport the analysis and the detection signal
feature
- 输入旋转机械振动信号,转速,采样频率。输出1-5倍转频幅值以及常见的13个时域特征-Enter rotating machinery vibration signals, rotational speed, the sampling frequency. 1-5 times the output amplitude and frequency transfer of 13 common characteristics in time domain
fenpin
- 输出比设定的时钟频率小8倍的时钟,实现分频功能,可用于芯片控制。-Output than the set of 8 times the clock frequency of the clock, to achieve frequency division function, can be used for chip control.
Sa
- function [Sx,f,alpha] = Sa(s,fs,M,N,read_f,del_f) 计算信号的循环谱 [Sx,f,alpha] = Sa(s,fs,M,N,read_f,del_f) 输入: s 序列 fs 采用频率 M 滑动频率窗长 N fft计算点数 read_f 可视频率(一般为载频的整数倍) del_f 可视频率间隔 输出: Sx 信号的循环谱 f 频率轴 alpha 循环频率轴-Cyclos
N-jifenpin
- 用verilog编写的N倍奇分频源码,大家可以参考一下哈哈哈。希望大神指正-With verilog written N times odd divider source code, you can refer to Ha ha ha. Great God hope corrected
12m
- 可以进行任意奇数偶数倍分频, yi jing yan zheng guo ,feichang haoyong-can be dived by any number ,odd or even.
test
- 利用接收端接收数据,并将数据进行多倍分频,之后利用串口调试助手显示接收数据-Data received by the receiving end, and many times the data division, after the use of serial debugging assistant displays the received data
VGA_disp
- clk divid 模块为分频电路,对50MHz 系统时钟进行分频产生50M/7Hz 的像素时钟。VGA control 模块为VGA 显示控制电路模块,在像素时钟的驱动下首先产生行频信号,而后对行频信号进行分频产生58Hz 场频信号。由于VS 与HS 信号具有严格的时序匹配,即VS 信号必须为HS 信号的整数倍,以保证在场频信号有效期间,能够完整数行的扫描,本设计利用对行频信号进行计数分频来产生场频信号。-Clk divid module for the frequency circuit,