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Freq_4
- 伺服电机编码器四倍频源程序,已经在工程中应用。非常有用。-it is important,it has been use in my project.i hope it is useful to everyone
pll
- 一个实现任意倍频的,输入参考频率未知的pll,已综合实现-frequency multiple rely on dpll,unknown reference input clock
CLOK
- 时钟分频。使用原有高频信号,将其10倍频,得到可用于八段数码管显示的扫描信号-Clock frequency. The use of the original high-frequency signal, frequency-doubling of its 10, the eight can be used to display the scanned digital signal
UART1
- C8051F130串口1测试程序,使用内部时钟,4倍频,100MHZ主时钟,波特率115200,发送什么数据,返回什么数据。发送数据采用查询方式发送,接收数据采用中断方式接收。-C8051F130 serial port a test program, using the internal clock, four multiplier, 100MHZ master clock, the baud rate 115200, send what data, what data to return.
52250440605_AB
- 基于CPLD 的光电脉冲码盘 信号四倍频电路设计-CPLD-based electro-optical pulse encoder signals four multiplier circuit design
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一,尽管在目前大部分设计中,广泛使用芯片厂家集成的锁相环资源,如altera 的PLL,Xilinx的DLL.来进行时钟的分频,倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
BPQ
- 倍频器-WE
RC
- 一、设计要求:1• 截止频率fH3d=1kHz 2• 带外衰减速率小于-30dB/10倍频 二、总体方案讨论:二阶RC有源滤波器的功能是让一定的频率范围内的信号通过,抑制或急剧衰减此范围内的信号,常用电路有电压控制电压源(VCVS)电路和无限增益多路反馈(MFB)电路,本设计采用电压控制(VCVS)电路,其中运放是通向输入,输入阻抗很高,输入阻抗很低,其优点是电路性能稳定,增益容易调节 -First, the design requirements: 1 R
multifreqvhdl
- 资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序,multifre1.vhd是倍频程序,multifre1.vwf是仿真波形文件,stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用,可以设置倍频数,修改实体参数N即可。-According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe tha
last
- 微机原理与接口技术———倍频信号发生器的的分析与设计 )主要任务:有一输入方波信号f0(50Hz~100Hz),时钟信号1MHz。要求输出信号: f1=2* f0, f2=4* f0。(自动跟踪) -Microcomputer Principle and Interface Technology--- Frequency Signal Analysis and Design of generator) Main tasks: there is a square wave input
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
Digitalpower
- 单片机设计了一种单片锁相倍频电 路,利用片内定时器和数字算法实现了对输入信号的同步 锁相和倍频,并输出倍频信号-: A single- chip digital phase- locking frequency- multi- plier circuit is designed based on the AT89c2051.The circuit can track the input signal in- phase and output the frequency- mu
1000hz
- 产生相应的标准的上升沿触发信号,并且有2倍频功能-The rising edge of the corresponding standard generated trigger signal, and features a 2 octave
chengxu
- 4位乘法器,4位除法器,K倍频的VHDL实现-Four multipliers, four dividers, K multiplier of VHDL
matlabs三分之一倍频程实现
- 通过三分之一倍频程滤波,然后绘制频谱图。
三分之一倍频
- 振动工程中振动级计算,试用于matlab计算。还有滤波程序。(The vibration stage calculation in vibration engineering is applied to Matlab calculation.)
jingxiang_beipin
- 实现编码器鉴向和4倍频,可用于电机测速等。(To achieve encoder and 4 times the frequency, can be used for motor speed and so on.)
Octave
- 倍频程分析,内有详细注释,程序生成四张图片,容易理解(Octave analysis, there are detailed notes, the program generates four pictures, easy to understand)
三分之一倍频程
- 三分之一倍频程程序,网上手机的octave(1/3 octave code from internet. usable for matlab 2016a)
abc
- 加速度振动1/3倍频程的matlab实现(make the realization of accelaretion to come out)