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oct3bank
- 1/3倍频程分析。有需要做这方面研究的同志们可以好好看一下。-1/3 octave analysis. There is a need to do research in this area can be a good look comrades.
sxh.ppt.tar
- 用芯片实现锁相环，初步掌握利用锁相环实现倍频的设计及调试方法。-Chip PLL with
cx6_4
- 振动信号频域处理方法____三分之一倍频程处理-Vibration Frequency Domain processing ____ one-third octave
20050416
- ML估计的高效的OFDM整数倍频偏估计算法-ML OFDM Frequency estimation method
The-low-loss-substrate-r
- AD9851的一些具体介绍这里就不说了。其DATASHEET上都说的很清楚。若看不懂E文，可以发E_M给我，我有中文资料。AD9851要写40位的控制子。其中前面32位就是频率控制子了。后面是有1个6倍频使能位，1个logic0位，1个POWER_DOWN位，还有5位相位模式字。这里我们只解决频率控制问题。也就是说在代码中本人只写了，32位的频率控制子，还有一个6倍频使能。其余的剩下几位由于没用到也就默认写为0了。AD9851可以用并和串俩中方式写入控制子。-The low loss subs
Matlab-Propagation-Code
- 超短激光脉冲传输：展宽、色散、自自相位调制、倍频、FROG，超短脉冲测量-Ultrashort laser pulse transmission: broadening, dispersion, since the self-phase modulation, frequency, FROG, ultra-short pulse measurement
AHB2APB_bridge
- 倍频算法实现了AHB-to-APB桥接器-An ahb2apb bridge with doubling algorithm
Encoder-Frequency-Doubling-
- 对主轴编码器脉冲固定倍频，首先4倍频，然后N倍频，要求转速波动小,内附参考资料-Fixed on the spindle encoder pulse frequency, the first 4x, then N frequency, requiring speed fluctuation is small, containing a reference
octave
- 三分之一倍频程，用于信号的能量分析，特别是噪声频道的能量-octave for noise analysis
PLL
- 9s12锁相环配置程序，1.5倍频。编译环境Codewarrior4.6-9s12 PLL configuration program, 1.5 octave. Build environment Codewarrior4.6
Small-multiplier
- 小型倍频器，简单的介绍了如何用verilog写倍频电路》-Small multiplier
octave
- 倍频程和三分之一倍频程滤波器设计源代码 希望大家多多交流-Octave and third octave filter design source code hope that we can exchange
pll20
- 能实现利用开发板上的锁相环实现倍频，程序思路清晰明了，易学习。-Use and development board to achieve phase-locked loop to achieve frequency, clarity of program ideas, easy to learn.
CPLD
- CPLD编程，处理两路编码器的信号，可以将信号四倍频。同时能够控制IO的输入输出信号。-cpld program
div2482233
- 倍频器的硬件描述语言编程，可以产生多种不同频率的时钟。-Multiplier hardware descr iption language programming, can produce a variety of different frequencies of the clock.
VHDL
- 基于VHDL的数字倍频器设计，这里只提供个算法，希望对你的编程有所启发。-Vhdl based on the number of times the frequency of the design,Here only to provide an algorithm, hope for your programming has been inspired.
MyDDR
- 分析FPGA如何控制DDR，这个方法是自己倍频而不是把倍频过程放进IPCORE里面处理-Analysis of how to control the FPGA DDR, this method is its frequency multiplier rather than the process inside the handle into the IPCORE
Manchester
- 单片机C8051F020对曼彻斯特编码的测频并产生同频同步的脉冲信号。需要两个单片机协同，频率为10-100KHz的整10倍频。-Manchester encoding C8051F020 microcontroller for frequency measurement and frequency synchronization with the pulse generated signal. Requires two microcontroller together, frequency o
program
- FFT A计权 倍频程分析 三分之一倍频程分析-F F T A w eight o c tave a n al o n e t hird o ctave
Untitled
- 三分之一倍频程处理程序,适用于声学及振动信号处理-the third singal