搜索资源列表
verilogpll
- 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
010919.pdf
- 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL descr iption and achieve functional simulation, followed by graphic shows
verilog全数字锁相环pll
- verilog全数字锁相环，用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
全数字锁相环
- 详细介绍数字锁相环的工程
FPGA-based-design-of-DPLL
- 采用VHDL设计的全数字锁相环电路设计，步骤以及一些详细过程介绍。-VHDL design using all-digital PLL circuit design, detailed process steps and some introduction.
verilog
- 采用用verilog语言编写的全数字锁相环的源代码。-Verilog language used by all-digital phase-locked loop' s source code.
DPLL2
- 全数字锁相环电路的研制，使用的是VHDL语言 -All-digital phase-locked loop circuit development, using the VHDL language
FPGA444555443
- 基于FPGA的全数字锁相环设计,内有设计过程和设计思想-FPGA-based all-digital phase-locked loop design, with the design process and design thinking
11112323
- 基于锁相环Top-down的建模方法在MATLAB环境下建立数字锁相环完整的仿真模型，并用SIMULINK对数字锁相环的仿真模型进行仿真。 -Top-down phase-locked loop based on the modeling method in MATLAB environment DPLL set up a complete simulation model, and use of digital phase-locked loop SIMULINK simulation mod
pll_verilog
- 全数字锁相环的verilog源代码,仿真已通过 -All-Digital Phase-Locked Loop verilog source code, simulation has passed
pll
- 摘要:叙述了全数字锁相环的工作原理,提出了应用VHDL 技术设计全数字锁相环的方法,并用复杂可编程逻辑器件CPLD 予以实现,给出了系统主要模块的设计过程和仿真结果。-Abstract: This paper describes the working principle of an all-digital phase-locked loop is proposed application VHDL technical design an all-digital phase-locked loo
2009
- 智能全数字锁相环的设计,基于FPGA实现。-Intelligent all-digital phase-locked loop design, FPGA-based implementation.
VHDLDPLL
- 基于VHDL 的全数字锁相环的设计，里面包含了最核心的程序。-VHDL-based all-digital phase-locked loop design, which contains the core procedures.
DPLL
- 全数字锁相环的verilog设计，已通过仿真验证能迅速锁定相位-Digital phase loop lock design with verilog
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
DPLL_verilog_a
- 用verilog语言描写设计的全数字锁相环，pDF资料-With the verilog language to describe the design of all-digital phase-locked loop, pDF information
AD-PLL
- 基于VHDL的全数字锁相环的设计与实现，quartusII的仿真程序。-DPLL based on VHDL Design and Implementation, quartusII the simulation program.
vhdl3
- 介绍一种基于VHDL 语言的全数字锁相环实现方法， 并用这种方法在FPGA 中实现了全 数字锁相环，作为信号解调的位同步模块。-Introduction of a language based on VHDL implementations of DPLL, and this method is implemented in the FPGA digital phase locked loop, as the signal demodulation of bit synchronizatio
verilog_PLL
- 全数字锁相环的verilog源代码，包括鉴相器，K变摸可逆计数器，加减脉冲器和N分频器。已经仿真实现。(All digital phase-locked loop Verilog source code, including phase discriminator, K variable touch reversible counter, add and subtract pulse and N frequency divider. Have been implemented by simula
dpll
- 数字全锁相环的介绍文章，讲述了数字锁相环的实现原理和实现步骤(The introduction of the digital full phase locked loop is introduced, and the realization principle and the implementation steps of the digital phase locked loop are described)