搜索资源列表
Temperature_Control_System
- 基于状态机的温度控制系统.vi 基于状态机的温度控制系统.vi-State machine based on the temperature control system. Vi
state_machine
- 状态机的描述，基于EasyFPGAv1.04 用状态机描述流水灯，状态机在1s的周期下流水灯，方向又sel控制-Descr iption of state machine, based on the state machine described by EasyFPGAv1.04 water lights, state machine at the cycle 1s under water lights, direction and control of sel
ADC0809
- 用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
3
- 有穷状态机，利用VC6.0编写蚂蚁找食的模拟程序-Finite state machine, the use of ants looking for food preparation VC6.0 simulation procedures
danpianjijianpansaomiaozhuangtaijishixian
- 单片机扫描状态机的程序实现，希望能帮助到有需要的朋友。-Single-chip state machine to scan the program, hoping to help a friend in need.
UART
- UART是一种广泛应用于短距离、低速、低成本通信的串行传输接口.由于常用UART芯片比较复杂且移植性差,提出一种采用可编程器件FPGA实现UART的方法, 实现了对UART的模块化设计.首先简要介绍UART的基本特点,然后依据其系统组成设计顶层模块,再采用有限状态机设计接收器模块和发送器模块,所有功能的实现全部采用VHDL进行描述,并用Modelsim软件对所有模块仿真实现.最后将UART的核心功能集成到FPGA上,使整体设计紧凑,小巧,实现的UART功能稳定、可靠. -UART is a wi
Finite_state_machine
- 压缩包为状态机在嵌入式单片机开发中的具体实现及应用，资料为网上整理收集-Compressed package for the state machine in single-chip embedded in the concrete realization of the development and application of finishing the collection of information online
Time_Triggered_system
- 本设计是我的毕业论文，将时间触发与状态机相结合，对单片机系统开发有一定启发-The design is my thesis will be time-triggered state machine with a combination of single-chip microcomputer system inspired the development of a certain
esm
- 详细介绍了三种高效状态机设计，其中还有PDF格式的说明（英文版）。-Detailed information on the status of the three high-performance design, including descr iption of PDF format (in English).
daima
- 状态机控制AD转换模块 该模块主要实现对MAX197的控制：根据设计需要对芯片进行初始化（包括写控制字选择输入电压值范围、选择通道以及工作模式），并把通道数送指示灯显示以及用键盘控制通道号（按一下，通道号加1，同时点亮相应的指示灯，循环使用个通道）；控制状态机的工作时序，并置两次采集到的数据为12位数据输出，并经过锁存进程来锁存数据，最后从锁存器中把输出数据-The state machine controls AD and changes the module this module ma
DVDT_MORE
- 基于FPGA有限状态机的数据采集系统，实现对高速AD转换的控制。-FPGA-based finite state machine of the data acquisition system for high-speed AD conversion control.
state_machine_design
- 这是讲解状态机的一个资料，里面讲解了摩尔和米勒状态机的设计实例，很详细且有实例。-This is a state machine on the information, which Moore and Miller explained the design of state machine instances, and there are examples of very detailed.
EP1C3_12_7_SPCTR
- 基于FPGA的信号采集及频谱分析，用VHDL编写，压缩包里是Quartus下的工程。AD采样用状态机实现，并存入LPM_RAM。设计了一个UART模块（也是状态机实现的），可将数据发到ＰＣ机上。-FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to
view
- 计时显示电路,6片七段数码管显示，内部计数器，通过Mealy型状态机实现-Time display circuit, paragraph 6 digital display, internal counter, through the Mealy type state machine to achieve
AOfficeClerk
- 状态机，描述了游戏里人工智能。状态之间的转换和描述。-State machine, described the game of artificial intelligence. Between state and descr iption of the conversion.
JohnFSM
- java相关的有限状态机的小机器人模拟程序-java-related small finite state machine robot simulation program
begoogatsme
- 讲述如何写好状态机的文档 给出了新颖的思路以及帮助读者上手的例子-On how to write state machine is given the document, as well as innovative ideas to help the reader-to-use examples
1
- 状态机：简单的状态变换功能，利用按键实现四个LED的轮回显示-State machine: a simple function of the state of transformation, the use of buttons to achieve the reincarnation of four LED display
ProducerConsumerExample
- 类似一个可乐销售机系统，LabVIEW网络讲坛《状态机》(State Machine)下集里面用作例子-Producer Consumer Example This particular example, a simulated soda machine, uses an event structure in the producer loop to register user input (depositingclicking on quarter, dime or nickel), an
fsm_mo10counter
- 模十计数器，状态机，用状态机控制计数器，00为保持，01为加1计数，02为+2计数-module10 counter