搜索资源列表
my_FIFO
- FIFO的verilog实现，成功通过验证，很好用需要的可以下载-Verilog implementation of FIFO successfully validated, the good need can be downloaded
my_VGA
- FPGA驱动VGA显示，通过验证，需要的可以下载。verilog实现-VGA display driven by the FPGA, through validation, need can be downloaded. verilog implementation
count4
- 四位加法器的Verilog实现，可以实现综合工具对其综合-Four adder Verilog implementation of their comprehensive synthesis tool can
1602lcd
- veriog HDL语言实现LCD1602显示-This program can drive the LCD1602 with verilog HDL language
verilog_xiyiji
- 为Verilog Hdl 代码实现自动洗衣机启动，复位，水洗，排水，脱水，等功能，并能显示洗衣机的工作状态-Code for the Verilog Hdl automatic washing machine start, reset, washing, drainage, dewatering, and other functions, and can display the working status of washing machine
VGA_COLOR_LINES
- 利用Verilog语言写的VGA彩条显示控制电路，显示器模式：1280X1024@60HZ.按下K1，K2键可控制彩条显示的模式-Use Verilog language is written VGA display control circuit, striped display mode: 1280 X1024 @ 60 HZ. Press the K1, K2 key can control the color display mode. Article
robust_fir_latest.tar
- RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh scr ipt in the run directory (notice that the run scr ipts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 differe
password
- verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。-verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the
odd_div
- 利用Verilog实现奇术次分频，这里只举了一个例子，但任意奇数次分频均可以用该原理实现。-Patients achieving the odd times using Verilog frequency, just to cite one example, but any odd frequency can be achieved with the principle.
test8
- 这是一个Verilog编写的VGA驱动程序，该程序在FPGA开发板上运行后，能在VGA显示上显示一个行走人的动画-This is a VGA driver in Verilog, the program running in the FPGA development board can display a person s walking animation on a VGA display。
Multifunction-digital-clock
- 这是多功能数字钟的Verilog源程序，此程序已经编译通过，可以使用-This is a multi-functional digital clock in Verilog source code, this program has been compiled by, you can use
Three-state-bidirectional-drive
- 这是三态双向驱动器的Verilog源程序，已经编译通过，可以直接使用-This is a tri-state bi-directional drive the Verilog source code, has been compiled by, can be used directly
Long-frame-synchronous-clock
- 这是长帧同步时钟产生的Verilog源程序，已经编译通过，可以直接使用-This is a long frame sync clock generated Verilog source code, has been compiled by, can be used directly
Variable-mode--counter
- 这是可变模加减计数器的Verilog源程序，已经编译通过，可以使用-This is the variable mode subtraction counter Verilog source code, has been compiled by, you can use
digital-clock
- 该程序是有verilog实现的fpga的交通灯 适用于cycloneII芯片 可供fpga初学者学习verilog语言时参考，不仅可以显示时钟 还能调整时钟分针秒针-The program is a verilog realize fpga of traffic light is applicable to cycloneII chips available for beginners to learn verilog fpga languages as reference, not only
VCDdecoder
- 基于GTK-wave做的verilog test bench语法解析器 解析vcd file. 俺自己写的-VCD (Value Change Dump) file is widely used in industry. A VCD file is an ASCII file, which contains header information, variable definitions and the value changes for specified variables, or
81
- 一个关于ＪＰＥＧ的例子，是用Verilog编写的，可以综合。-A case of JPEG is written in Verilog, can be integrated.
SDRAM_TEST
- 用Verilog硬件描述语言驱动SDRAM，内有完整可实现源代码，且还有现象说明-With the Verilog hardware descr iption language driven SDRAM, can be realized within the complete source code, and there is the phenomenon described
SRAM_TEST
- 用Verilog语言驱动SRAM，内有SRAM可实现源代码以及对应现象说明-With the Verilog language-driven SRAM, SRAM can be realized within the source code and corresponding descr iption of the phenomenon
triangular_wave
- sr flipflop verilog you can simulate it in any eda tool