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visualitzador7segments-20170516T144823Z-001
- Code in VHDL of a segments visualizer (used for a clock)
contador_v4-20170516T144731Z-001
- VHDL for a counter used in a clock.
counter (2)
- This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.
kebenchengxu
- VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
数字时钟
- 基于VHDL语言编写的数字时钟程序，经验证，可以用硬件实现(Based on VHDL language digital clock program, verified, you can use hardware to achieve.)