搜索资源列表
sdram_vhdl_lattice
- sdram接口的vhdl实现,适用于lattice的FPGA，内含状态机和各个模块的具体实现-SDRAM interface VHDL realization lattice applied to the FPGA, containing the state machine and the concrete realization of each module
EDA
- 地址译码，状态机的编写，三态输出，布司乘法器-Address decoder, the preparation of state machines, three-state output, cloth Division Multiplier
aczz
- AC算法 用指针实现 用指针指向状态机的状态变量-AC algorithm implementation using pointer with pointer to state machine of the state variables
zhuangtaiji
- 这是一个最最常用的用vhdl写的状态机，几乎哪儿都用得到-a very good state machine
actree
- 这里是我个人编写的状态机的实现的程序，-Here are my personal preparation of the state machine implementation of the procedures, 111
a
- 这里是我个人编写的状态机的实现的程序，-Here are my personal preparation of the state machine implementation of the procedures, 111
state
- 十种状态机例子，简单易懂，是学习fpga的好帮手-Dozens of examples of state machine, easy to understand, is a good helper fpga study
VHDLexample
- 步进电机控制，直流电机控制，加法器，状态机等等经典的VHDL例子程序。-Stepper motor control, DC motor control, adders, state machines, etc. The classic example VHDL procedures.
jiaotongdeng
- 这程序是利用状态机来控制交通灯verilog码-This procedure is the use of state machine to control the traffic lights verilog code
parallelstatemachineinCS
- 在客户端和服务器架构中，平行状态机的使用，使用python实现的，最多可以有20个客户连接到服务器上，服务器将会验证客户端状态的改变-This demonstration illustrates the use of parallel statemachines in a client-server implementation.
c73a2ceb-09a5-4366-83ea-78b08c6200eb
- jtag TAP控制状态机代码 verilog VHDL-jtag TAP state machine code
statemachine
- 用verilog HDL实现状态机的设计-Verilog HDL make the state machine come true
user-interface
- User Interface的设计,包括显示DAQ,Movie,Flash,Website.状态机的设计-the code of User Interface
IOcontrol
- 输入输出控制的状态机，verilog HDL源码-Input and output control state machine, verilog HDL source
StateMachine
- 工作流 状态机 审批工作流 wf+Asp.net approval stateMachine-wf+Asp.net approval stateMachine
electroniclock
- 1）能完成开锁功能 2）能实现设置密码的功能 3）用有限状态机的方法编程 4) 作业提交时间：在第14周周日前提交-1) to complete the unlock function 2) set a password to achieve the functions of 3) by the method of finite state machine programming 4) submitted the operating time: 14 weeks in the fir
SDRAMVerilogHDL
- FPGA控制串行AD（AD0804）,状态机实现，可以根据该程序实现数字电压计，数字温度计的设计-FPGA serial control AD (AD0804), state machine to achieve, you can program according to the number of voltage, the digital thermometer design
15AlteraIP
- FPGA控制串行AD（AD0804）,状态机实现，可以根据该程序实现数字电压计，数字温度计的设计-FPGA serial control AD (AD0804), state machine to achieve, you can program according to the number of voltage, the digital thermometer design
division
- 带同步复位的状态机,适用于VHDL语言操作,对于初学者或是深入的人都适宜-replacement_state_bar
stop_watch
- 使用状态机实现的秒表，另外包含计数器功能-The use of state machine to achieve the stopwatch