搜索资源列表
amba3core.rar
- amba3 sva 完全验证的代码，有verilog的和systemverilog的,amba3 sva fully validate the code, and the Verilog and SystemVerilog
System_Design_and_Implementation_of_AXI_Bus
- AMBA AXI资料，台湾硕士论文，网上收集-AMBA AXI, Taiwanese master' s thesis, on-line collection of
apb_slave
- AMBA 2.0 APB Example- SRAM -AMBA 2.0 APB Example- SRAM
AirFoil_grid
- This Fortran Program develop for NACA0200 Airfoil Axi-symmetric grid generation. The grid is clustered in x. Program is basic level for under graduate students.
AMBAaxi
- This AMBA® AXI Protocol v1.0 Specification-This is AMBA® AXI Protocol v1.0 Specification
unix
- IBM axi学习PPT,详细的命令操作过程及结果显示-IBM axi learning PPT, and the detailed results of the command operation
axi_slave_latest.tar
- AXI is AMBA4 compliant. code this code is a verilog imp lementation of AXI slae
axi_bfm_ug_examples.tar
- axi_bfm_ug_examples axi bus function model user guide examples-axi_bfm_ug_examples axi bus function model user guide examples
axi_master_latest.tar
- axi 总线 设计 和 仿真， 可以在设计中直接运动， 提供完整源代码和仿真文件， 用vhdl 语言实现。-axi bus design and simulation, you can directly exercise in design, providing full source code and simulation files, using vhdl language.
axi_master
- 自己写的 AXI master code-AXI master code
AXI_slave
- 自己写的 AXI slave 代码，是ARM 内嵌的 总线通信-AXI slave code
AirFoil_grid
- This Fortran Program develop for NACA0200 Airfoil Axi-symmetric grid generation. The grid is clustered in x. Program is basic level for under graduate students.
uvm_axi-master
- axi uvm vip, verification model -axi system verilog
AXI4与AXI3的区别
- AXI4与AXI3的区别,l例如：AXI4对burst length进行了扩展：AXI3最大burst length是16 beats,而AXI4支持最大到256 beats，但是仅支持INCR burst type超过16 beats，exclusive access也不能超过16beats;。(the different of AXI4 and AXI3)
axi_master_latest.tar
- AXI_Master_verilog_code
AXI_testv1.00
- 添加ILA逻辑分析仪观测AXI总线时序，根据时序可以自行对AXI总线进行应用。(Adding ILA logic analyzer to observe the time sequence of AXI bus)
zynq_dma_test
- pl dma 驱动, 自测试文件，需要将两端stream对接即可(pl AXI dma driver, In block design , connect mm2s with s2mm.)
new.v
- 状态机写的axi slave，模式较少，基本功能齐全，轻便,仿真综合通过(AXI4 slave programmed by state machine approach)
AXI&APB2SPI
- APB总线转SPI接口模块SV代码以及AXI总线转SPI接口模块SV代码(SV code of APB bus to SPI interface module and SV code of Axi bus to SPI interface module)
axi slave model
- axi slave model,verilog源码