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Cyclone_II_FPGA_sch
- altera 飓风二代开发板的原理图，pdf格式 -altera hurricane of the second generation development board schematics, pdf format
Bufor
- Circular buffer using a cyclone memory ( Quartus II and VHDL .)-Circular buffer using a cyclone memory ( Quartus II and VHDL .)
LCD_test
- this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
audio_latest.tar
- Audio Codec(ADPCM 1-Bit) The code is ready for Altera Cyclone-II DE1 Starter board and it is tested, you can modify codes and use them in any project. Core Descr iption: Sampling Frequency: 44100Hz Channels: Stereo Bit-rate: 1 Bit Per Sa
digital_clk
- VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA