搜索资源列表
ISE_chinese
- 通俗的介绍了ise的使用方法，对vhdl和verilog开发的初学者来说是不错的选择-popular introduction to the use of the method ideally, the VHDL and Verilog development of the newcomer is a good choice
在ISE下调用计数器IP核
- 非常简单的计数器，在ISE下调用计数器IP核，使用verilog开发得到的。-Very simple counter, under the invocation counter in the ISE IP cores, development has been the use verilog.
FIFO
- 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
sdr_sdram_control
- 一个SDRAM控制器，verilog语言设计，并在ISE上仿真实现。（内部包含多个verilog程序）-sdram-controller,use verilog langguage,it s run sucessfull
digitalclock
- Verilog数字时钟 实现24小时的监控，用七段码显示出来，包含时序图等 在ISE下仿真-digital clock Verilog
sdram
- 在ISE开发环境下的单速率SDRAM简单读写控制器设计，用的是verilog硬件描述语言-ISE development environment in a single-rate SDRAM controller read and write simple design, using the verilog hardware descr iption language
serialcomuniactionsource_files
- 用于FPGA与232通信的编程设计，用VERILOG语言编写的，在ISE中仿真-232 communications for FPGA programming and design, using the VERILOG language in ISE Simulation
ttraafficLighr
- <p>交通灯状态机的实现，用verilog HDL编程与开发，Xillinx ISE 6仿真，在实际电路中的到验证． 已通过测试。</p> -<p> The implementation of the traffic light state machine, using verilog HDL programming and development, Xillinx ISE 6 simulation, to verify the actual circui
Mstateei
- 米勒解码器的状态转换模块。用verilog语言编写写，ISE为开发环境 ，经测试可直接使用。 -Miller decoder state transition module. Verilog language writing, ISE development environment has been tested and can be used directly.
calculator
- 基于赛灵思的spartan-3e开发板的语音智能计算器的设计，开发语言verilog，开发软件ISE，可以根据ucf文件理清引脚关系。应用者需要对开发板和fpga设计有一定的了解！-Development board based on Xilinx spartan-3e voice smart calculator design, development languages Verilog, developing software ISE, according to
DigitalWatch
- 用verilog数字钟，并且在ise上验证，可以显示分秒，并且可以对分和秒进行调整-Verilog digital clock, and verified in ise, can display every minute, and you can adjust the minutes and seconds
LED_TEST
- Verilog的LED闪烁程序，xilinx ISE开发环境-Verilog LED flashes, Xilinx ISE development environment
CRC16_8
- 利用ISE软件采用Verilog HDL语言编写CRC码，每时钟处理8bit数据，在输入序列后最终加上16位校验码。-Using Verilog HDL language CRC code, 8bit data processing per clock, after the final of the input sequence plus 16 checksum.
adc0809
- ADC0809转换器的verilog版本,运用在ISE上，直接可用（注意没有考虑频道问题），结果显示在数码管里（十进制）-Verilog version ADC0809 converters, used in the ISE, directly available (note does not consider channel problems), the results are displayed in the digital tube (decimal)
ISEadder
- 利用Verilog语言，基于ISE，设计加法器-ISE adder
CPU(4)
- 基于ISE XILINX14.7开发的单周期CPU的基础指令实现代码 VERILOG-VERILOG implementation code base based on single-cycle instruction CPU ISE XILINX14.7 development of
clk_div3
- 基于XIlinx ISE，用Verilog语言实现3分频电路，适合初学者-Based XIlinx ISE, Verilog language using the frequency dividing circuit 3, suitable for beginners
黑金Sparten6开发板Verilog教程V1.6
- 黑金xilinx ise fpga verlog 教程(Black gold Xilinx, ise, FPGA, verlog tutorials)
ddr3_test
- ddr3相关代码和基于ISE仿真调试，板级调试(DDR3 related code and simulation debugging based on ISE, board level debugging)
i2s_top
- i2s接口fpga实现，工作在主模式，ISE和vivado下已验证(I2S interface FPGA implementation, working in the master mode)