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4b5b_6b8b
- 4b5b和6b8b扰码接口程序，在CCS6000下测试通过。-4b5b 6b8b scrambler and the interface procedures, the CCS6000 under test.
scrambler
- 通信系统中扰码的实现，采用Matlab的S函数-Communication System Scramble the realization of Matlab function S
scrambler
- Something which is important for those want to design scrambler
PAPR
- Obtain the CDF plots of PAPR from an OFDM BPSK transmission specified per IEEE 802.11a specification Per the IEEE 802.11a specifications, we 52 have used subcarriers. Given so, the theoretical maximum expected PAPR is 52 (around 17dB). However, tha
scrambler
- 一个x^43+1解扰的函数，以前的师兄留下的，希望有人能用得上。-a descrambler about x^43+1.
[FileScrambler]
- File Scrambler for Data-Encryption and Data-Decription
scrambler-descrambler
- 5th order scrambler-descrambler function as described in the scrambler wikipedia article.
scrambler
- python scr ipt to crypt data using scrambling
signal_chain
- signal chain lte includes scrambler descrambler mapper demapper transform precoder check it its very good th-signal chain lte includes scrambler descrambler mapper demapper transform precoder check it its very good thxxx
dvbcsa
- DVB-CSA complete (de)scrambler source code
scrambleraencoder
- 包含16位的并行扰频器和解扰器，其方程是1+x14(x的14次方)+x15(x的15次方)，还有测试代码，另外还有自己编的8b10b编码，自己已经测试过了-Contains 16 bit parallel scrambler and descrambler, the equation is 1+ x14 + x15 , and the test code.Besides, there is 8b10b coding which is tested。
scramb_descramb
- scrambler and descrambler
data_scramble
- 实现802.11a发射机中基带处理的扰码部分，经过测试可以正常工作。-Achieve 802.11a baseband transmitter scrambler part, tested to work properly.
qieting
- matlab环境下的窃听信道建模，包括crc校验编码，三种（QPSK,16QAM,64QAM）不同的调制方式仿真，加入扰码增强抗窃听能力。-Matlab environment eavesdropping channel modeling, including the CRC check code, three kinds of (QPSK, 16 qam and 64 qam) different modulation mode simulation, join the scrambler e
report-hardware-Scrambler changed
- study of scramblers and descramblers with the help of its practical implementation in lab. This report also encloses the net results by the scramblers and descrambles implemented using D-Flip Flop
加扰器解扰器设计
- 加扰器解扰器设计,组合逻辑电路可以选用下述不同的逻辑类型来实现：互补CMOS结构、有比电路、差 分共源-共栅电压开关逻辑（DCVSL），传输门逻辑、互补传输晶体管逻辑（CPL）或动态电 路结构，也可以是以上不同类型结构的混合。(Scrambler/ descrambler design)