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chA
- phase frequency detector verilog
seqdetector1001.v.tar
- 1001 sequence detector in verilog code for mealy state machine
Verilog-Code
- Verilog source code by James Patchell: - Delta Sigma Modulator for doing Digital->Analog Conversion - Aquad-bquad phase detector - Uart Reciever - Uart Transmitter - One shot
work
- 这里面包含了从易到难的6个很经典的verilog例子，有序列检测器，3位乘法器，数字报表等-It contains from easy to difficult six very classic verilog example, a sequence detector, three multiplier, digital statements, and so on
xuliefashengqi
- 序列发生器和检测器的verilog代码编写。-Sequence generator and sequence detector realization with verilog
Fsm
- 基于verilog的FSM设计，设计“101001”的序列检测器；包括testbench文件-The FSM based verilog design, design " 101001" sequence detector including testbench files
src
- SEQUENCE DETECTOR IN VERILOG