搜索资源列表
m序列
- Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
rng_opencore
- opencore, random number generator, verilog
DDS
- 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
PTN_gen
- this pattern generator source code(verilog)-this is pattern generator source code(verilog)
fir
- fir 滤波器 Systems generator 实现并转化为verilog语言-fir Filter Systems generator to achieve and into verilog language
lfsr.v.tar
- linear feedback shift register for generator in verilog code for random sequence generation.
fibonacci_gen.v.tar
- fibonnaci generator in verilog code
xinhao
- 基于verilog的数字信号产生器，包括三角波、方波、正弦波，频率可调。-Verilog-based digital signal generator, including a triangle wave, square wave, sine wave, frequency adjustable.
xulie_100111
- 用verilog语言编写的并且仿真通过的100111序列发生器的工程文件夹-the generator of 100111
xuliefashengqi
- 序列发生器和检测器的verilog代码编写。-Sequence generator and sequence detector realization with verilog
final_sawtooth
- sawtooth generator in verilog
UART-DISPLAY
- lcd 显示，Verilog语言，串口接收数据，并在LCD中显示，波特率9600，包括主文件，LCD控制文件，波特率发生文件-lcd display Verilog language, serial port to receive data, and the LCD display, baud rate of 9600, including the master file, the LCD control file, the baud rate generator file
DCM
- CCD SENSOR 驱动信号发生器，基于VERILOG HDL-CCD SENSOR driving signal generator, based on VERILOG HDL
lutsr
- verilog design of lut sr random number generator
NandBuffer
- verilog编写，含三路正弦信号发生器，三路数据乒乓缓存模块。乒乓缓存读写控制采用三段式状态机实现。-The project contains a 3-channel sine generator and a 3-channel ping-pong buffer which is written in verilog. The write and read control of buffer is implemented in 3-segment FSM.
DDS_FPGA
- 任意波形发生器FPGA实现，Verilog语言编程，试验板为DE0-Arbitrary Waveform Generator FPGA implementation, Verilog language programming, test panels of DE0
Sender
- verilog langurage to generate random numbers
mcode
- 附有m码产生verilog文件和测试文件，以及详细说明。读者可根据说明配置任意级m序列发生器(With M code, Verilog files and test files are produced and detailed. The reader can configure an arbitrary m sequence generator according to the instructions)
Verilog-Generator-of-Neural-Networks
- 利用DE0nano开发板实现了对用的卷积神经网络(The CNN algorithm is implemented.based FPGA)