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aes_inv_cipher_top
- aes ip core, 128 bits
AES-IP-core-key-expansion-module
- AES IP核密钥扩展模块设计与仿真（设计过程及程序，测试程序）-AES IP core key expansion module design and simulation (the design process and procedures, test procedures)
AES--IP-core-architecture-design
- AES算法分析及其IP核体系结构设计（包括设计过程及代码）-AES algorithm analysis and its IP core architecture design
AES-IP-core-encryption-module-design
- AES IP核加密模块的设计与仿真(包括设计过程及代码)- the AES IP core encryption module design and simulation
AES-IP-core-control-module-design
- AES IP核的控制模块的设计与仿真以及系统集成与仿真-AES IP core design and simulation of the control module and system integration and simulation
A-compact-AES-core-with-on-line-error-detection-f
- This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logi
te7022
- TEL7022程序，TXT。TEL7022程序TEL7022程序(USB 2.0 Full-Speed compliant supported USB Audio Class 1.0 16/24 bit Resolutions supported 8/16/32/44.1/48/96 KHz sampling rates supported 2-input channels and 2-output channels supported by one I2S pairs