异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory

Circular buffer using a cyclone memory ( Quartus II and VHDL .)-Circular buffer using a cyclone memory ( Quartus II and VHDL .)

FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL