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verilog for uart
- 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver / transmitter (UART) can be programmed to control computer attached to the serial device interface microchips.
用verilog硬件描述语言编写的fft算法
- 用verilog硬件描述语言编写的fft算法，很是经典，和大家共享，希望能对大家有所帮助。,Verilog hardware descr iption language with the preparation of the fft algorithm, it is a classic, and we share the hope that it can be helpful to everyone.
miaobiao 用verilog VHDL描写的秒表程序
- 用verilog VHDL描写的秒表程序，可以显示百分秒，秒和分。-Verilog VHDL with the descr iption of a stopwatch program, can display the arc, seconds and points.
CLOCK
- 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
lfsr
- 用LSFR实现计数功能，可以减少对寄存器和少一个加法器，涉及verilog的人来说-Used to achieve LSFR counting functions, can be reduced to a few registers and adders, the people involved in Verilog
lcd1602-verilog
- 基于QuartusII的LCD1602-Verilog 源代码，可以直接应用于FPGA开发板。-QuartusII based on the LCD1602-Verilog source code, can be directly applied to FPGA development board.
ask10
- This a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.-This is a simple MIPS processor datapath written in VERILOG hardware language. You can
CPU_verilog
- 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
frequencycounter
- 一个简单大家容易看的懂的频率计设计程序，可以实现自动换挡功能。-A simple and easy to see to understand all of the frequency counter design program that can automatically shift feature.
seven_seg_decoder
- ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment
binary_to_bcd
- this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres
rom_prf_gen
- 用ram存储顺序，用此方法也可以实现其他的顺序数据，代码用verilog编写-Ram memory with the order can be achieved using this method also the order of the other data, write code using verilog
Verilog
- 该代码是Veriloghdl语言实现的串口通信，经过FPGA板子下载验证通过，读者可以使用-The code is Veriloghdl language of the serial communications, after verification by FPGA board download, readers can use
i2c-IPcore
- 一个I2C 接口的verilog 代码，经过测试，可以用的-Verilog code for an I2C interface, tested, can be used
Descrambler
- ofdm中相位检测的Verilog程序，很不错，可以在Xilinxfpga上运行。-phase detection in ofdm Verilog program, very good, you can Xilinxfpga run.
sourceInsight-lan
- souceinsight软件的语言解析文件，用于高亮关键字，开发浏览代码时，有所帮助。-DeviceIOControl, vc in io shows how to direct the operation of the underlying need friends can learn about.
CAN--Verilog-code
- can协议转换控制器的Verilog代码，在Quartus软件上测试通过-The CAN protocol conversion controller Verilog code, through the test on Quartus software
fft1024 verilog代码
- fft1024 verilog 代码 可以编译成功 建议下载学习(The fft1024 verilog code can compile successful Suggestions for download learning)
20 CAN总线实验
- 基于can总线的，Verilog源代码分享，可以在Z7030芯片开发板进行演示。(Based on the CAN bus, Verilog source code sharing, can be demonstrated in the Z7030 chip development board.)