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System watchdog verilog code
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there is a text file of code for 8 bit up counter in verilog.
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Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
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基于Verilog HDL
1、div为分频模块,晶振50M,目的是得到1HZ
2、cnt为异步清零，同步加载，同步使能的十二进制计数器。-4-Bit Binary Up Counter with Asynchronous Clear, Synchronous Load, and Asynchronous En.
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verilog source code of programable counter
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附件包括两个内容1.采用Verilog编写的的十进制计数器的ISE工程2.代码文档一份。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Appendix includes two contents of 1 written by Verilog decimal counter of the ISE project a 2 code document. The software platform is ISE13.3, the hardware platform is Spart
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verilog code on frequency counter
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格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
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