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A9
- clock divider, has multiple versions of clock divider for the de2 board
3FSK.vhd
- 利用MAXPLUS作为仿真工具，用VHDL语言编程，采用频率键控法实现3FSK调制。对输入的系统时钟分别进行2分频，4分频和8分频得到这3种频率。通过对数字基带信号进行双二进制编码得到3个电平值，把它们作为三选一开关，来分别选择不同的频率值、选择不同的信号，从而实现3FSK调制。-As a simulation tool used MAXPLUS using VHDL language programming, using frequency shift keying modulation me
Clock_Divider_top
- Simple clock divider
fenpinqi
- 利用microwave office实现分频器的实验框图及性能分析-Achieved using microwave office divider block diagram and performance analysis of the experimental
diver
- 利用VHDL语言设计了五位除法器 实验环境为maxplusII 内有各个模块详细的程序代码 以及相应的模块截图-Designed using VHDL, five divider within the experimental environment maxplusII detailed code of each module and the corresponding module screenshot
Crossover
- 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
div32
- 基于verilog的分频器 23分频器 可更具需要修改成任意偶数分频器-23 divider verilog-based crossover can be even more need to modify the divider into any
clkdiv
- -- Clock divider of generic width (default = 4 bits) -- based on counter from Library of Parameterized Modules (LPM) -- Accepts clock signal at clk_in -- Output clk_out has frequency of clk_in/(2^width) -- Specify width in GENERIC MAP when in
StaticSplitWnd2
- vc 固定分割窗口的分隔线\StaticSplitWnd2的程序源码-vc fixed split window divider \ StaticSplitWnd2 the program source code
StaticLineDemo
- vc——使用Picture控件实现分隔线\StaticLineDemo-vc- use the Picture control to achieve divider \ StaticLineDemo
StaticSplitWnd2
- vc——固定分割窗口的分隔线\StaticSplitWnd2-vc- fixed split window divider \ StaticSplitWnd2
StaticSplitWnd2
- vc——固定分割窗口的分隔线\StaticSplitWnd2的程序源码,值得一看！-vc- fixed split window divider \ StaticSplitWnd2 the program source code, worth a visit!
StaticSplitWnd2
- 固定分割窗口的分隔线\StaticSplitWnd2\StaticSplitWnd2.rar,很不错的vc源码，希望对大家有所帮助。-Fixed split window divider \ StaticSplitWnd2 \ StaticSplitWnd2.rar, very good vc source code, we want to help.
chufaqi
- 电子学课程设计--有符号5位整数除法器设计与制作-Signed5 bit integer divider design and production
fenpin27
- VHDL硬件语言系统时钟27分频程序，可用于各种时钟分频参考-VHDL hardware language system clock frequency of the program, 27 points can be used for a variety of clock divider reference
clk_div
- 对时钟进行分频，进行了偶数分频。改实验代码已经试验运行过，可以运行。-Clock divider, and even divide. Change the experimental code has been test run, you can run.
dcm25test
- 采用建立IP核的办法，DCM实现25M分频-The establishment of IP nuclear approach, DCM 25M frequency divider
op_div_5
- VHDL写的奇数次分频电路，占空比为50 .-VHDL to write odd frequency divider circuit, the duty cycle is 50 .
divider
- verilog很省资源的除法器，（用减法，需要时钟）验证通过-Province resources division, verified by
yibutongxun
- 用VHDL实现的异步通讯模拟程序和报告。分为控制器，接收器，发射器三部分，其中应用到了异步串行通讯控制器的设计以及非整数分频器的设计。-Asynchronous communication using VHDL simulation procedures and reporting. Divided into the controller, receiver, transmitter three parts, which applied to the design of asynchronous