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fenpin
- 用VHDL写的一段很小的任意整数分频器，可以设置任意整数数值，来获得所要的分频值-Use VHDL to write for some small arbitrary integer divider can be set to any integer value, so as to obtain the desired divider value
Div
- 非常好用的小数除法器，verilog开发的。quartusii下综合通过-Very easy to use fractional divider, verilog developed. quartusii under comprehensive by
13.11_div_golschmidt.vhd
- A vhdl code for goldschmidt divider- A vhdl code for goldschmidt divider,,,,,,
sederhana
- Clock Divider Altera DE-1 and Its Application in a simple logic circuit
vhdl--of--traffic-light
- 十字路口的交通灯vhdl控制程序，其中包括分频器、交通灯控制器和主程序三部分。-Crossroads of traffic lights the vhdl control procedures, including the three parts of the divider, traffic light controller and main program.
100jinshuqi
- 100分频计数器，已验证，作为vhdl初学者借鉴，也可在源程序的基础上进行修改-100 binary divider counter
huhu
- 基于FPGA的密码锁设计，其中分频电路VHDL程序代码-FPGA-based password lock design which divider circuit VHDL code
74845002vhd_divider
- 除法器，用于求余用算，流水线性运算，， -Divider, for the remainder used to count
CAL
- 一款简单的计算器,可以加减乘除。但是除法会有小数不精确的问题。-A simple calculator, subtraction, multiplication and division. But the problem of inaccurate divider there decimal.
shu_ma_guan4
- 基于span3E进行数码管显示的控制，时钟采用了计数分频器的设计，将50MHz的是时钟作为系统时钟-Based span3E control, digital display clock count divider design, the 50MHz clock as the system clock
fp
- 用FPGA Verilog 语言编写的一个简单的分频器，内部有详细的中文注释，希望对初学者有益。-The FPGA Verilog language written in a simple divider, there are detailed notes in Chinese, hope useful for beginners.
Verilog1
- 实现了cic分频功能，分频系数D可变2~32，代码用verilog编写，其中输入数据写入主程序中，便于后人testbench的编写-Cic divide divider coefficient D variable from 2 to 32, the code is written in verilog input data is written to the main program, to facilitate future generations testbench preparation
1freqdiv
- 使用VHDL代码高速而有效的实现了频率的分频，整个工程全部上传，bit文件可以直接下载-VHDL code fast and effective frequency divider, the whole project upload all bit file can be downloaded directly
clock1
- 该代码实现的是使用VHDL语言编程实现的FPGA上的时钟分频。通过修改代码中的参数改变FPGA的输出时钟频率。-The code implements the VHDL language programming on the FPGA clock divider. Changed by modifying the parameters in the code of the output clock frequency of the FPGA.
fenpindianlu
- 分频电路包括2MHZ5MHZ10MHZ50MHZ100MHZ-The frequency divider circuit comprises 2MHZ5MHZ10MHZ50MHZ100MHZ
gonglvfenpeiqi
- 北邮 大三下 微波实验 AWR 功率分配器 2013-BUPT junior next experiment AWR microwave power divider 2013
divider
- 偶数 奇数 小数分频器的设计,很详细实用，希望对大家有帮助-even odd frequency_divider
verilog_fenpin
- verilog分频 verilog分频 verilog分频 -Divide Divide verilog verilog verilog verilog divider divider divider verilog verilog divider
verilog_fenpin0
- 这是一个verilog分频代码，代码比较简洁.-This is a divider verilog code, the code is relatively simple.
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器，利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa