搜索资源列表
frequency-divider
- 利用FPGA实现分频器功能并完成LED数码管静态和动态显示-Using FPGA to achieve crossover features and complete LED digital control static and dynamic display
diviseur
- it s descr iption in VHDL code of divider. this is complex arithmetic operation
streamline_div
- 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
fenpinqi
- 基于vhdl语言编写的分频器程序，可实现五十分频。-Based divider vhdl language program, can achieve five very frequently.
cntr_4bit
- This the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit-This is the 4 bit VHDL CODE which is a synchronous clock divider is added to provide the delay ot this circuit
compare
- 八位字节比较器，四选一多路选择器，二分频电路-Octet comparator 4 election more than one way selector, the second divider circuit
fenpin
- 通用整数分频器，可以分频占空比为1:1，也可以为任意占空比-General integer frequency divider, can divide frequency and duty ratio of 1:1, also can be for any duty ratio
ViewSpliter
- 进行窗口的自动分割，并能自动设置分隔条的位置和分割窗口的大小。-Automatic segmentation of window, and can automatically set the size and location of the divider partition window.
pulse8
- 任意占空比的8分频电路,也可以任意分频，经过优化，很稳定-Arbitrary duty 8 divider circuit may be arbitrarily divided optimized, very stable
divider8
- 使用硬件描述语言设计8分频器，并将结果通过七段数码管显示-The hardware descr iption language is used to design the 8-frequency divider, and the result is displayed by 7-segment LED
fenpin
- 分频器程序，可以进行分频，精度高，很不错！-Divider program can be frequency, high accuracy, very good! Ha ha ha
bile-segmentation
- Using vc to write file segmentation, Use vc to write the file divider
源代码
- 这是内部有10位ADC的一个简单应用，这个电路最多测量30 V DC，可以应用在台式电源或各种系统中的面板仪表。 PIC16F676的内部adc与一个电阻网络分压器用于测量输入电压，用数码管来显示电压值，频率在50HZ左右 在原理图中的47K看到和10K电位连接分压器配置。在默认情况PIC微控制器ADC参考电压设置到VCC（+ 5V在这种情况下），分出最大射程30伏到5伏这样的分压器。(This is a simple application with 10 bit ADC insi
AD9512_SPI_Config
- 用户可以通过各分频器改变一路时钟输出相对于其它时钟输出的相位，这种相位选择功能可用于时序粗调。(The user can change the clock all the way through the frequency divider output relative to other clock output phase, the phase selection function can be used for timing coarse adjustment.)
clock
- there's a clock divider for DE2 altra board clock (50MHz)
ds819_div_gen
- DS819数据手册 LogiCORE IP Divider Generator v4.0(LogiCORE IP Divider Generator v4.0)
PBBSZM1
- 用vc写的文件分割器,Use vc to write the file divider(Using vc to write file segmentation, Use vc to write the file divider)
CAV
- CStringArray* CCollectDoc::DevideStr(CString ItemFieldStr,char divider)
guan 27
- 分频器分频为2Hz后，使计数时间变为0.5秒一个，将此时的频率传给计数器，计数器计数的变化时间就变为0.5秒一变然后再用数码管显示出数字的变化，即可得到一个从0~9变化的计时器。 文件名为随便起的项目名称，使用时如果更改需要和代码中的实体名等一起更改(Frequency divider for 2Hz, the counting time is 0.5 seconds a, the frequency to change the time counter counter becomes 0.
ZZBKCHI
- 用vc写的文件分割器,Use vc to write the file divider()