搜索资源列表
fifo源程序
- fifo源程序，VHDL编写~具有一定的参考价值~-source code of a fifo, writen in VHDL, will be useful to some extent as a reference
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
fifo
- 同步fifo的原代码,给出了经典的同步fifo原代码，希望对大家有所帮助-synchronous fifo code
fifo
- a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
fifo
- 完成进程调度，页面置换算法中先进先出算法（FIFO）的源代码，对学习操作系统很有用的~-The completion of the process of scheduling, the page replacement algorithm in the FIFO method (FIFO) of the source code, useful for learning the operating system ~
MaxiCOM
- Unfortunately Microsoft has never paid much attention to the serial port. In the Windows API it is just regarded as a file, and in the first version (1.1) of the .NET framework (managed code) there was no support for serial communication. Fortunately
USB-slavefifo
- 在上位机上实现cy68013的slavefifo模式传输代码-In PC mode to achieve cy68013 of slavefifo transmission code
FIFO
- 页面置换算法的实现源码。主要为OS初学者提供参考。-Page replacement algorithm implementation source code. The main reference for the OS for beginners.
FIFO
- vhdl code for first in first out
fifo
- 同步fifo的verilog代码，很好的资料，值得学习-Synchronous fifo verilog code, very good information, it is worth learning
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
fifo
- 同步FIFO设计一个同步FIFO，该FIFO深度为16，每个存储单元的宽度为8位，要求产生FIFO为空、满、半满、溢出标志。请采用可综合的代码风格进行编程。-Synchronous FIFO design a synchronous FIFO, the FIFO depth is 16, the width of each memory cell is 8, required to generate the FIFO is empty, full, half full, the overflow
OV7670-Camera-Module-with-FIFO
- it is a source code to drive camera
fifo
- 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
FIFO
- 关于异步FIFO的原码程序，采用格雷码改善了二进制码带来的不足- ON划词翻译ON实时翻译 On asynchronous FIFO the original code procedures, the use of gray code improves deficiency caused by binary code
FIFO
- FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL
FIFO
- 提供的是页面置换算法中最简单的先进先出策略的java代码实现(The Java code implementation of the simplest FIFO policy in the page replacement algorithm is provided)