搜索资源列表
Simulator
- 基于VC++的MIPS五级整数流水线模拟系统，附有设计文档与源代码。-VC++ for MIPS based on five integer pipeline simulation system, with design documents and source code.
mips_quick_tutorial
- MIPS assembly tutorial for beginners.give you some basic understanding of MIPS architecture and assembly language
eetop.cn_spim
- mips 模拟器. 里面有 ppt 说明 讲解。-Mips emulator
Simulators
- 基于VC++的MIPS五级整数流水线模拟系统，附有设计文档与源代码-VC++ for MIPS based on five integer pipeline simulation system, with design documents and source code
Kien_truc_bo_lenh_MIPS
- Kien truc bo lenh MIPS
DLX
- DLX实现，实用Visual C++编程，思想为MIPS体系结构，可以考察系统仿真的性能和指标-DLX implementation, using Visual C++.
fft3780_assembly
- 3780点FFT MIPS汇编程序，进行了多级优化，包括算法-3780-point FFT MIPS assembler, and multi-level optimization, including algorithm
risc
- RISC是一种执行较少类型计算机指令的微处理器，起源于80 年代的MIPS主机（即RISC 机），RISC机中采用的微处理器统称RISC处理器。这样一来，它能够以更快的速度执行操作（每秒执行更多百万条指令，即MIPS）。因为计算机执行每个指令类型都需要额外的晶体管和电路元件，计算机指令集越大就会使微处理器更复杂，执行操作也会更慢。 -RISC is a microprocessor performs fewer types of computer instructions, originat
MMIPPS-xmodeeI
- MIPS架构Xmodem与Ymodem源码程序源码，与与tftp齐名常用网络通讯协议 -Xmodem and Ymodem source of the MIPS architecture program source code, and tftp par common network communication protocols
sort
- MIPS code for Selection Sort
mips_ejtag
- Mips Ejtag Code! Mips Cpu 调试必备工具！-Mips Ejtag
x86_Dhystone_2.1
- 可在x86上運行及量測cpu效能mips的軟體-It could work on X86 plateform, and measure porformance
strLen
- 用MIPS实现求字符串的长度，只用r0, r1, r3三个寄存器, 字符串从内存地址0开始存储-MIPS implementations find the length of the string, using only r0, r1, R3 three registers, strings from memory address 0 storage
code
- 是用verilog写的带uart的简单controller，使用的是mips指令，用modelsim仿真，波形正确-With uart verilog write a simple controller, use the mips instruction the modelsim simulation, waveform correctly
MIPS
- 51单片机软件实验的代码。有内存操作、数制与代码转换、算数运算、比较和查表。-51 MCU software experimental code. Memory operation, the number system and code conversion, arithmetic, and compare and look-up table.
MIPS-2
- 51单片机的硬件实验：包括I/O控制实验、定时器计数器实验、按键与显示实验、并行AD、DA实验-51 microcontroller hardware experiment: I/O control experiments, the timer counter experiments, buttons and display experiment, parallel AD, DA experimental
cache
- 基于MIPS思维方式，verilog语言，简单的cache 控制器设计，状态机共分4个状态，同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
ALU
- MIPS ALU written using Verilog HDL. Computer structure project
cpu
- MIPS流水线CPU的工作原理和设计方法-The design and implementation of the pipelined CPU
hiuart2t_ins
- 适合于MIPS指令集的MCU测试，尤其是模拟部分的测试，例如V2P-test for MIPS instruction