搜索资源列表
MIPs
- 这是mux计数器的源代码,其中包含testbench 的源码。-This is the mux counter source code, which contains testbench source.
lcd
- 基于mips的pic32的lcd显示 显示字符支持滚屏换行-Based on the pic32 mips lcd display shows scrolling newline character support
m3u8streamtv_2.9_all
- Python开发的扩展件,用于基于MIPS Cpu 的Enigma2固件下流媒体播放。所有采用MIPs处理器的机顶盒都可以安装。-m3u8 extension for Enigma 2
CPUdesign
- 32位MIPS五级流水CPU,实现了基本指令功能,结构完整,讲解清晰。-32bitCUP design
micro-op_cpu
- MIPS 微程序多周期cpu,mips的部分代码实现-MIPS cpu micro-program multi-cycle
CoolPlayer-RC2
- wince下mips架构播放 wince下mips架构播放-wince for mips wince for mips wince for mips
Virtual-Machine
- C++模拟mips处理器,能执行mips二进制代码,支持大部分mips指令,可选文字显示和图片显示两种模式-C++ simulation mips processor can execute binary code mips, support most mips instruction, optional text display and picture display modes
LFYY_cpu
- 建议CPU五级流水,带有指令寄存器cache,处理数据冒险-code for cpu mips with cache
scmips_cpu
- 自己写的单周期mips CPU和测试工程-Write your own single cycle mips CPU and test engineering
pipeline_mipscpu
- 运用Verilog语言实现MIPS五级CPU的功能,能下载实现-5-level MIPS CPU based on Verilog
fpga_pc_software
- 计算机组成原理课程实验使用软件,Thinpad教学机教学实验软件 实现mips代码到机器代码之间的转换 实现本机和FPGA板的通信,将机器代码送入 可在本机编写代码送入fpga板的sram中,fpga板的cpu会运行-Computer architecture course experiment using software, Thinpad teaching machine teaching experiment software mips code into machine co
multi_cpu
- 用verilog语言编写的简单多周期CPU代码,在Sparten3板上可运行。实现了加、减、与、或、非等MIPS指令。-Verilog language with a simple multi-cycle CPU code can be run in Sparten3 board. Realization of add, subtract, and, or, not, etc. MIPS instruction.
mips-code-to-machine-code
- 汇编代码转成机器码——对输入有几点要求:指令是小写;一行只能有一条指令;每行开头不能有空格,必须一上来就是操作符,后面可以有空格;立即数只处理十进制数;输入-1代表程序结束-Turn assembly code into machine code- there are several points of entry requirements: command is lowercase line can only have one instruction beginning of each l
project3
- 计算机组成原理 Logisim完成单周期处理器开发 支持指令集MIPS-Lite2-Principles of Computer Organization Logisim complete development support single-cycle instruction set processor MIPS-Lite2
MIPSCPUverilog
- mips流水线CPU的实现,用的是verilog语言,描述了整个cpu的过程。存储、指令、处理等。-mips CPU Verilog
CPU1
- 一个简单的多周期的基于MIPS的CPU设计-cpu VHDL
CPU
- 32位MIPS指令CPU,实现31条指令,并且附带LED,七段数码管,VGA,键盘,UART等外设接口-32 MIPS instruction CPU, a 31 instructions, and comes with LED, seven-segment LED, VGA, keyboard, UART peripheral interfaces
machine_code_to_mips
- 机器码转换为汇编码,将指令存在计算机内的编码及机器码转换为mips汇编语言-machine code to mips
openmips
- 一个开源mips处理器verilog 源码-wishbone interface wishbone interface
Operating-System
- 用Xshell上基于C语言开发小型mips操作系统。-EXPLOID A TINY MIPS OPERATION SYSTEM BASED ON C USING XSHELL