This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave

支持主从模式的、可综合的SPI verilog代码-Supports master and slave mode SPI communication module can be integrated RTL code

spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)