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verilog for uart
- 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver / transmitter (UART) can be programmed to control computer attached to the serial device interface microchips.
u-uart
- UART verilog TX/RX OpenCores share
uart verilog
- 串口verilog UART,源码；串口verilog UART,源码
S7_PS2_RS232
- 利用cpld作为cpu控制器将ps2中取得按键值通过串口传送给pc机-cpld verilog ps2 UART
uart_rx
- Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL
uart.v.tar
- uart Universal asyncronous receiver and transmitter verilog code
Verilog-Code
- Verilog source code by James Patchell: - Delta Sigma Modulator for doing Digital->Analog Conversion - Aquad-bquad phase detector - Uart Reciever - Uart Transmitter - One shot
UART
- verilog版UART，非常实用，设计中可以直接实用，不能自己写代码-verilog coding for UART
1.UART
- 该代码主要实现UART的串行通信，针对的是RS232芯片，同时包含了verilog和VHDL编写的程序-The code UART serial communication, RS232 chip, also contains a program written in verilog and VHDL
UART-DISPLAY
- lcd 显示，Verilog语言，串口接收数据，并在LCD中显示，波特率9600，包括主文件，LCD控制文件，波特率发生文件-lcd display Verilog language, serial port to receive data, and the LCD display, baud rate of 9600, including the master file, the LCD control file, the baud rate generator file
uart
- FPGA上的verilog 的uart实现方法-FPGA on the verilog uart implementation
uart
- uart设计的verilog代码，支持双工的串行传输，兼容synopsis 的DW_uart的编程模型-verilog code uart design, support duplex serial transmission, compatible synopsis of the programming model DW_uart
uart
- 该源码包是uart串口协议的verilog语言模型，主要包括了3个部分：波特率产生模块，uart接收模块，uart发送模块。(The source package is UART serial protocol Verilog language model, including 3 main parts: baud rate generation module, UART receiver module, UART transmission module.)
UART
- UART loopback测试实例，接收PC端发送的UART数 据，原数据返回给PC端，即loopback功能(The UART loopback test instance receives the number of UART sent by the PC side According to the original data returned to the PC side, that is, the loopback function)
Verilog_uart
- 锆石科技 用Verilog实现uart通信，文件包括模块和顶层文件，直接解压缩在quartus上编译即可。(Zircon technology Verilog with uart communication, the file includes the module and the top file, the direct decompression can be compiled on the quartus.)
UART_source_code
- uart verilog code for nexys2 fpga borad
FS4LPWPIXGFMOS1
- uart transmitter using verilog.checked in vivado 16.2 version
uart_fifo_n
- verilog 带fifo的串口收发模块(verilog uart with fifo)
verilog
- lcd1602 12864显示程序代码，串口传输数据代码(lcd1602 12864 code,UART code.)
FPAG UART Verilog
- FPGA实现URAT，实现异步串口收发控制(FPGA implements URAT to realize asynchronous serial port and transceiver control)