搜索资源列表
enc
- HDB3编码器 使用VHDL编制 对于基带传输很有用的程序-HDB3 encoder using VHDL preparation for baseband transmission useful procedure
conv_vhdl
- 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
viterbi_1
- low power convolution encoder and Viterbi decoder using vhdl code
encoder
- Encoder is written in VHDL. This is simulated using ISIM and synthesized with ISE
hardh264
- h.264 encoder using vhdl