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Assignment(VLSI)
- Verilog model codes for beginners
KL-algorithm.v.1.0.2
- Kerlinhan-Lin VLSI bi-partition 算法。 C++程序，一个cpp,一个.h. Kerlinhan-lin是二分图的最小权值算法，经常使用在VLSI电路自动化设计的物理paratition上，在其他的图形问题中也有应用。-Kerlinhan-Lin bi-partitioning algorithm. Mainly used for VLSI CAD design
lfsr
- Ruby LFSR 模拟程序。 可以自动生成任意位数的VLSI test pattern用于VLSI TEST. 含有两种lfsr,等概率LFSR和加权LFSR.-LFSR simulator based on ruby language.
multiplayer-vlsi
- this code is used for designing multiplier by using verilog code
Area-Delay-Power-Efficient-Carry-Select-Adder-usi
- Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 pape
VLSI Architecture for Real-Time HD1080p
- 3d-hevc虚拟视点合成算法；硬件实现.VSRS算法(3d-hevc virtual view synthesis algorithm; hardware implementation;.VSRS algorithm)
Microwind
- A good images made by microwind for VLSI
智能优化算法
- 优化技术是一种以数学为基础，用于求解各种工程问题优化解的应用技术。作为一个重要的科学分支，它一直受到人们的广泛重视，并在诸多工程领域得到迅速推广和应用，如系统控制、人工智能、模式识别、生产调度、VLSI技术和计算机工程等。鉴于实际工程问题的复杂性、约束性、非线性、多极小、建模困难等特点，寻求一种适合于大规模并行且具有智能特征的算法已成为有关学科的一个主要研究目标和引人注目的研究方向。 20世纪80年代以来，一些新颖的优化算法，如人工神经网络、混沌、遗传算法、进化。(Optimization te
ALUYEDEK
- alu circuit design for vlsi and 4 bits alu
3. Comparator
- EXCLUSIVE OR and EXCLUSIVE NOR gates may be viewed as 1-bit comparators. Figure 1(a) shows an interpretation of the 74x86 XOR gate as a 1-bit comparator
Chopper_IA
- A small-area low-ripple chopper instrumentation amplifier (IA) using a sample-and-hold circuit
CMOS Nested-Chopper
- A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV.
CMOS_IA
- A low-noise CMOS instrumentation amplifier intended for low-frequency thermoelectric microsensor applications
Current Feedback_IA
- A power-efficient current-feedback instrumentation amplifier (CFIA) with high gain accuracy.
Feedback_IA
- A precision general-purpose current-feedback instrumentation amplifier (CFIA) that employs a combination of ping-pong auto-zeroing and chopping to cancel its offset and 1/f noise.
Low-Power CMOS Acquisition
- A low-power analog acquisition front-end circuit for Wireless Body Area Network (WBAN).
Microcantilever
- An analog signal processing integrated circuit for microcantilever array has been designed for pressure measurement in biomedical applications.
Binary Stack counter
- Designing of stack counter using binary logical input and multiplier design integration
watermark
- SPATIAL DOMAIN WATERMARKING WITHOUT CONTENT ALTERATION
jeas_reversable-vedic-multiplier
- reversible logic is mainly used to achieve low power. peres gate HUG gate is used to design a vedic multiplier. reversible gate we can give n numbers of input and we can get n number of output