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statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
11.2
- 推荐下载,verilog处理器设计实例.体现了结构描述和寄存器传输描述的应用 -recommend downloading Verilog processor design examples. Reflect the structure descr iption and register transfer described in the Application
8.10
- 强烈推荐下载,verilog状态机实例.可以在modelsim下运行. -strongly recommend downloading Verilog state machine example. In modelsim running.
Example-3-1
- 该程序是用quartus II作为开发工具，用verilog语言编写，实现全加器功能的实例。对初学者很有意义