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statemachine_mult
- veilog实现的状态机乘法器.可以参考-veilog achieve the state machine multiplier. Can reference
statemachine11.2
- 推荐下载,verilog状态机实例.体现了流水线思想的应用 -recommend downloading Verilog state machine example. Pipeline reflects the thinking of the application
8.10
- 强烈推荐下载,verilog状态机实例.可以在modelsim下运行. -strongly recommend downloading Verilog state machine example. In modelsim running.
FSM_program
- 用于协议状态机的编程参考，可以用于协议设计。-agreement for the state machine programming reference design can be used in the agreement.
有限自动机C++
- 利用状态表和有限自动机的运行原理编制程序，使得程序能够识别一个输入串是否为一个有效的符号串-tables and the use of the limited state of the automatic machine operation principle procedures, making procedures to identify whether an input string as a symbol effective Series