搜索资源列表
divid5_VERILOG
- VERILOG实现无分频时钟，包括测试文件，经过验证可用-VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication
clk_div
- 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
onesecond
- 用verilog实现将50M晶振分频，得到1M的功能，本人已经用Quarter9.0运行成功。-To achieve with verilog 50M crystal frequency, get 1M' s functions, I have run successfully with Quarter9.0.
div32
- 基于verilog的分频器 23分频器 可更具需要修改成任意偶数分频器-23 divider verilog-based crossover can be even more need to modify the divider into any
calculator
- 这是一个设计16位计算器，运用Verilog HDL语言编写，可以实现简单的加减法计算。并且可以在Xilinx91i上仿真。其中 top.v文件为目录，calculator.v为计算器设计，display.v为显示设计，divclk.v为分频设计，keypad.v为键盘设计，并且testkeypad.v为检测程序。-design a 16-bit calculator using the Spartan 3 FPGA on the Digilent circuit board, with an
fenpin20
- verilog中实现20分频-verilog achieve 20 points in the frequency ........
verilog
- 一些基本的Verilog 代码 包括基本的分频器设计，交通灯设计，自动售货机设计，有限状态机的设计-Some basic Verilog For freshman
4fenpinverilog
- verilog语言编写的4分频设计模块及仿真-Verilog language crossover design module and simulation
VerilogFreq-div
- Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法-Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide
Three-divider
- 用verilog硬件描述语言实现的三分频器-Three divider
divFrequencyverilog
- verilog写的任意分频的实现代码，可根据需要配置使用-divide verilog write any implementation code, based on the need to configure
fp
- 用FPGA Verilog 语言编写的一个简单的分频器，内部有详细的中文注释，希望对初学者有益。-The FPGA Verilog language written in a simple divider, there are detailed notes in Chinese, hope useful for beginners.
Verilog1
- 实现了cic分频功能，分频系数D可变2~32，代码用verilog编写，其中输入数据写入主程序中，便于后人testbench的编写-Cic divide divider coefficient D variable from 2 to 32, the code is written in verilog input data is written to the main program, to facilitate future generations testbench preparation
Verilog-crossover-design
- Verilog分频器设计分频器是FPGA设计中使用频率非常高的基本单元之一-Verilog crossover design
verilog_fenpin
- verilog分频 verilog分频 verilog分频 -Divide Divide verilog verilog verilog verilog divider divider divider verilog verilog divider
verilog
- verilog分频程序，适合初学者，任意分频！-divider verilog procedures, suitable for beginners, arbitrary frequency!
3FP
- 一个三分频verilog模块，可以用来学习基本结构。-A three points frequency verilog module can be used to study the basic structure.
ex1_clkdiv
- Verilog语言编写，通过此代码控制CPLD输出任意偶数倍分频-Verilog language, through this code control CPLD any even multiple output divider
random frenquency division
- verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)
timer_se
- 数字时钟可以显示分、秒，并通过按键进行复位；数字时钟由四个基本模块组成，顶层模块、分频模块、计数模块、译码显示模块。（1）分频模块 分频器将开发板提供的6MHz时钟信号分频得到周期为1s的控制信号，控制计数器改变状态。（2）计数模块：秒钟和分钟利用两个模60的BCD码计数器实现。计数器分为高4位与低4位分别控制低4位每秒钟加1，变化状态为0~9，低4位状态变化到9时，高4位加1，变化状态为0~5。秒钟计数达到59时，分钟低四位从1开始，每59秒加1，低4位状态变化到9时，高4位加1，变化状态为0