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yfifo
- 一个异步FIFO，自己写的。初学多交流学习进步快！-An asynchronous FIFO, write your own. Beginners to learn and exchange more rapid progress!
uartfifo
- 串口fifo的实现~实现了串口功能以及异步fifo，经过调试和功能仿真-The implementation of the serial fifo ~ serial port functionality as well as asynchronous fifo, after debugging and functional simulation
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
fifoVerilog
- 设计一个异步FIFO，完成数据平滑功能，FIFO的深度为256，宽度为8位，实时给出读空和溢出指示，写时钟为带间隔的100MHz，读时钟为5MHz，代码为了便于读阅，存放在word文档，可直接拷贝到quartus或者ise编译平台下使用-Design an asynchronous FIFO, complete data smoothing function, the depth of the FIFO 256, and the width is 8 bits, real read empty
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
fifo
- 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
FIFO
- 关于异步FIFO的原码程序，采用格雷码改善了二进制码带来的不足- ON划词翻译ON实时翻译 On asynchronous FIFO the original code procedures, the use of gray code improves deficiency caused by binary code
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modifications.
fifoas
- 异步时序的FIFO，实现了异步逻辑的电路，可综合，通过了验证-Asynchronous timing FIFO, implement asynchronous logic circuits can be integrated through the verification
Syn_FIFO
- 异步FIFO verilog fifo代码-Asynchronous FIFO verilog fifo Code
asyncfifo
- 异步fifo的设计，内含完整代码，亲测可用-Asynchronous fifo design, containing the complete code, pro-test available
async_fifo
- 异步FIFO verilog 代码 复位到空，读侧以及写侧复位均可以使两侧同时复位，且基本同时放开。-ayschronized FIFO verilog code
FIFO Design
- 异步fifo设计经典文章，可作为异步fifo设计基础导读(Asynchronous FIFO design classic article, can be used as the basis for asynchronous FIFO Design Guide)
fifo
- 学习Clifford_E论文之后完成的异步FIFO，可以完成异步时钟下的数据同步(After learning Clifford_E paper, the asynchronous FIFO can be completed under asynchronous clock data synchronization)
异步FIFO设计
- 经典的异步FIFO设计，First Input First Output的缩写，先入先出队列，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令。(Classic asynchronous FIFO design)