搜索资源列表
time_div
- IP 分频器 可以通过输入参数而自动调整分频数-IP divider input parameters can be automatically adjusted at the frequency
mod_m_counter
- frequency divider, it generates clock waveform from another clock divide by any divider
divhalf
- 本分频器不仅可以达到任意的整数分频，还可以达到半分频，例如3.5分频-The divider can be achieved not only arbitrary integer frequency, but also semi-sub-band can be achieved, for example, frequency of 3.5 points
Freq_Divider
- frequency divider using verilog
music_disply
- 音乐播放器 中的数控分频器 后续还需要添加一个分频的电路-Music player in the follow-up of NC divider also need to add a sub-frequency circuit
Crossover
- 分频器的设计，包含普通分频器和占空比为50 的奇数分频 ；4位乘法器的VHDL程序；-Crossover design, including general divider and the duty cycle of 50 of the odd frequency 4-bit multiplier VHDL procedures
dcm25test
- 采用建立IP核的办法，DCM实现25M分频-The establishment of IP nuclear approach, DCM 25M frequency divider
op_div_5
- VHDL写的奇数次分频电路，占空比为50 .-VHDL to write odd frequency divider circuit, the duty cycle is 50 .
frequency-divider-graphic-design
- 数字系统EDA 多级分频器图形设计 熟悉和掌握MAX+PlusⅡ的编译、仿真操作。-The multi-level divider graphic design of digital systems EDA familiar with and master MAX+Plus Ⅱ compilation, simulation operation.
FPGAfrequency-divider
- 一种基于FPGA的分频器实现，讲的很详细，很实用，希望能帮助您。-A kind of the frequency divider based on FPGA realization, speak very detailed, very practical, the hope can help you.
1freqdiv
- 使用VHDL代码高速而有效的实现了频率的分频，整个工程全部上传，bit文件可以直接下载-VHDL code fast and effective frequency divider, the whole project upload all bit file can be downloaded directly
fenpindianlu
- 分频电路包括2MHZ5MHZ10MHZ50MHZ100MHZ-The frequency divider circuit comprises 2MHZ5MHZ10MHZ50MHZ100MHZ
DivFrec
- Employ IP cores in VHDL to describe some functions Module digital clock manager , in this case to create a frequency divider
frequency-divider
- 利用FPGA实现分频器功能并完成LED数码管静态和动态显示-Using FPGA to achieve crossover features and complete LED digital control static and dynamic display
fenpin
- 通用整数分频器，可以分频占空比为1:1，也可以为任意占空比-General integer frequency divider, can divide frequency and duty ratio of 1:1, also can be for any duty ratio
divider8
- 使用硬件描述语言设计8分频器，并将结果通过七段数码管显示-The hardware descr iption language is used to design the 8-frequency divider, and the result is displayed by 7-segment LED
AD9512_SPI_Config
- 用户可以通过各分频器改变一路时钟输出相对于其它时钟输出的相位，这种相位选择功能可用于时序粗调。(The user can change the clock all the way through the frequency divider output relative to other clock output phase, the phase selection function can be used for timing coarse adjustment.)
guan 27
- 分频器分频为2Hz后，使计数时间变为0.5秒一个，将此时的频率传给计数器，计数器计数的变化时间就变为0.5秒一变然后再用数码管显示出数字的变化，即可得到一个从0~9变化的计时器。 文件名为随便起的项目名称，使用时如果更改需要和代码中的实体名等一起更改(Frequency divider for 2Hz, the counting time is 0.5 seconds a, the frequency to change the time counter counter becomes 0.
ise
- 在ise软件上，用VHDL语言，设计的数字跑表，可以两位计数，含分频器，计数器(In the ISE software, using VHDL language digital stopwatch design, can two counts, including frequency divider, counter)
plj
- 使用vhdl语言原件例化设计数字频率计，并用6位7段数码管计数。模块包括：十进制计数器，6位10进制计数器，Reg24 锁存器、Fp 分频器、Ctrl 频率控制器、Disp 动态显示。(The digital frequency meter is designed by using VHDL language as an example and counted by 6-bit 7-segment digital tube. Modules include: decimal counter, 6