搜索资源列表
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
fifo
- 同步fifo的原代码,给出了经典的同步fifo原代码，希望对大家有所帮助-synchronous fifo code
fifo
- a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
qianru_EZWJL
- EZW举例 该源代码包含有6个文件： EZW.H － EZW编码器头文件 EZW.C － EZW编码器文件 MATRIX2D.H MATRIX2D.C － 编码器数据结果定义和数据操作 FIFO.H FIFO.C － 扫描方式定义：先入先出原则 LIST.H LIST.C － 零树结构定义和操作 UNEZW.C － EZW解码器 这里，读者重点要掌握的是EZW.C和LIST.C中的内容，充分理解零树的概念。 -EZW example of t
fifo_for_beginner
- 新手学习用的FIFO源代码，希望能帮到有用的人-Novice to learn to use the FIFO source code, useful for people who want help to
FIFO
- vhdl code for first in first out
fifo
- 同步fifo的verilog代码，很好的资料，值得学习-Synchronous fifo verilog code, very good information, it is worth learning
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
fifoVerilog
- 设计一个异步FIFO，完成数据平滑功能，FIFO的深度为256，宽度为8位，实时给出读空和溢出指示，写时钟为带间隔的100MHz，读时钟为5MHz，代码为了便于读阅，存放在word文档，可直接拷贝到quartus或者ise编译平台下使用-Design an asynchronous FIFO, complete data smoothing function, the depth of the FIFO 256, and the width is 8 bits, real read empty
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
fifo
- 同步FIFO设计一个同步FIFO，该FIFO深度为16，每个存储单元的宽度为8位，要求产生FIFO为空、满、半满、溢出标志。请采用可综合的代码风格进行编程。-Synchronous FIFO design a synchronous FIFO, the FIFO depth is 16, the width of each memory cell is 8, required to generate the FIFO is empty, full, half full, the overflow
SDRAM_LCM_PROJECT
- sdram源代码，输入16数据位数据到sdram，再传送到fifo，通过uart端口发送出去。-sdram source code, data input 16-bit data to sdram, then transmitted to the fifo, sent through uart port.
OV7670-Camera-Module-with-FIFO
- it is a source code to drive camera
fifo
- 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
FIFO
- 关于异步FIFO的原码程序，采用格雷码改善了二进制码带来的不足- ON划词翻译ON实时翻译 On asynchronous FIFO the original code procedures, the use of gray code improves deficiency caused by binary code
PIC18F_ECAN_FIFO
- Microchip Pic18F code example to enable the Mode2/FIFO example. Very little accurate information is available to enable this mode.
Syn_FIFO
- 异步FIFO verilog fifo代码-Asynchronous FIFO verilog fifo Code
FIFO
- first input and first output vhdl code
FIFO
- FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL