搜索资源列表
alu_Verilog
- It is the code for implementing the project titled "The Reconfigurable Instruction Cell Array(IEEE 2008)".
DFF_using_BhvrlTech
- 数据选择器verilog源程序，此方法简单明了，容易实现-To Build a project with the Function of DFF---MC10131
BISTProject
- BIST test doing project, in verilog.
frequency
- 用verilog编写的频率计项目，能够自动换量程-Written in verilog frequency meter project, to wrap range
final-project
- Verilog 的Branch和Jump指令的实现 添加了MUX和额外的ALU-Verilog Branch and Jump instructions achieve add the MUX and additional ALU
ALU
- MIPS ALU written using Verilog HDL. Computer structure project
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
counter
- 采用VERIlOG HDL语言设计的一个加法器项目，简单可靠，并把其中测试平台程序加入其中-VERIlOG HDL language designed using an adder project, simple, reliable, and to join the program in which the test platform
LEDhuadong
- LEDhuadong，是基于quarterii写的Verilog程序，可以下载到板子上，是一个工程文件-LEDhuadong, is based quarterii write Verilog program that can be downloaded to the board, is a project file
ds1302_seg7
- 使用Verilog完成DS1302的驱动，工程已经经过测试，可直接使用。-DS1302 using Verilog complete drive, the project has been tested and can be used directly.
counter2
- 附件包括两个内容1.采用Verilog编写的的十进制计数器的ISE工程2.代码文档一份。采用的软件平台是ISE13.3，硬件平台是Spartan-3E。-Appendix includes two contents of 1 written by Verilog decimal counter of the ISE project a 2 code document. The software platform is ISE13.3, the hardware platform is Spart
project
- 睿行fpga开发板配套例程，verilog版本-ruixing fpga vhdl example
ADS8329
- ADC芯片ADS8329数据采集的verilog代码，已经用在工程中，没问题。(ADC chip ADS8329 data acquisition Verilog code, has been used in the project, no problem.)
MAC_MPEG2_AV
- Mac mpeg verilog xilinx project
vga
- 该文件夹是一个关于vga接口的FPGA源码工程(This folder is a FPGA source project on the VGA interface)
project
- 完整的FPGA例程，可在平台上跑，对初学者有很大的帮助(The complete FPGA routine, running on the platform, has a great help for beginners.)
AC PROJECT DHL DOC
- ac project source code for beginner
sumexp
- e是输入，sum_e是输出，cnt_in是累加数据的个数。这个模块是我（新手）一个项目中用来累加exp(x)的一个模块。(E is the input, the sum_e is the output, and the cnt_in is the number of accumulative data. This module is a module that is used to add exp (x) to a project in my (novice) project.)
electrical lock
- 一个用Verilog写的电子锁工程，带testbench。(An electronic lock project written in Verilog with testbench.)
TLT_drive
- 关于彩屏（TLT）驱动的编写，实现彩屏的显示，工程在quartus13中建立，包括了仿真设计(About the color screen (TLT) driver's preparation, the realization of the color display, the project was established in quartus13, including the simulation design.)