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FPGA-based Viterbi convolutional coding and decoding of the Research and Implementation-Convolutional code encoder and Viterbi decoder design
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编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
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利用viterbi演算法去解出convolution code
包含兩種方法，一種是soft一種是hard,soft是求內積最大，而hard則是求最小hamming distance。-Convolution edcoder Viterbi decoder algorithm
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The source code simulating the encoder and decoder of a rate 1/2 systematic convolutional code using the Maximum Likelihood Viterbi algorithm.
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low power convolution encoder and Viterbi decoder using vhdl code
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使用matlab进行卷积码编/译码器的仿真
进行Viterbi译码算法的编写-Write code using matlab convolution encoder/decoder Viterbi decoding algorithm simulation performed
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用matlab m语言书写的归零卷积码的编码和译码程序(Convolutional code encoding and decoding procedures in matlab)
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