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c
- Implement of SRM Position Check ing Ar ithmetic Ba sed on FPGA
0511xtgxs
- 2005年11月系统分析师考试试卷(转自csai)
chengjiaoliang
- 培养金融意识希望大家都能从中有所收获挣大钱过快乐的生活
傅立叶变换
- fft变换verilog代码
Fortran 90 for Scientists and Engineers及程序
- 写得较细的一本编程参考书及程序
coachspec2
- zoran 数码相机设计文档资料，原版spec-zoran spec for 2
Api Rp 550-Installation Of Refinery Instruments And Control Systems
- Api Rp 550-Installation Of Refinery Instruments And Control Systems -Section 2 - Level: API 550 is one of the reference standards of API, but it is not accesible from standard manager programs. this is one of APII 550 sections about Level sensor inst
DEAP2.1软件分享
- DEAP2.1软件分享，对数据包络分析很好用-GOOD DEAP,对数据包络分析很好用
该代码实现了IEEE802.11p模块
- 该代码实现了IEEE802.11p模块，将其添加进ns2中，便可实现802.11p的模拟仿真。,The code has IEEE802.11p module, to add it into ns2, the will to achieve simulation of 802.11p.
RC500_sch_pcb.rar
- RC500制作读卡器的全套电路及PCB版图,RC500 reader produced a complete set of circuit and PCB layout
NS2-Adhoc.NS2上模拟ad hoc网络的经典协议
- NS2上模拟ad hoc网络的经典协议，如DSDV ,AODV 和DSR，模拟的方法过程都阐述的很清晰。,NS2 to simulate the classic ad hoc network protocols, such as DSDV, AODV and DSR, simulation method process is set out very clear.
AD7705.7705的接口及应用电路
- 7705的接口及应用电路，详细描述了7706的应用,7706interface
BlueLab-3.4.2.绝对经典的蓝牙开发工具软件
- 绝对经典的蓝牙开发工具软件，自带软件包。,Absolute classic Bluetooth development tools, software, comes with the package.
HMM.rar
- hmm代码 隐马尔科夫模型 用于手势识别等,hmm code hidden Markov model for gesture recognition, etc.
DNP3.rar
- 详细介绍了DNP3通信规约(数据链路层),便于开发相应的软件。,Details of DNP3 communication protocol (data link layer), to facilitate the development of corresponding software.
ICETEK-VC5509-C.rar
- ICETEK_VC5509_C的硬件原理图，泰瑞公司开发的针对TI C5509A DSP的评估版。包含xilinx FPGA 及语音解码芯片TLV320AIC23等的连接，可借鉴性强 ,ICETEK_VC5509_C hardware schematics, Terry developed for the TI C5509A DSP evaluation version. Contains xilinx FPGA and voice decoder chip TLV320AIC23 conne
vcusb.rar
- 用vc写的，用于读取usb口数据的文档，里面有部分代码,Written by vc, usb port for reading data files, there are some code
amba3core.rar
- amba3 sva 完全验证的代码，有verilog的和systemverilog的,amba3 sva fully validate the code, and the Verilog and SystemVerilog