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mac_controller
- 用verilog编写实现的以太网控制器(MAC)源码,解压后用ISE打开工程即可。-Prepared using verilog implementation Ethernet Controller (MAC) source code, open the project after decompression can be used ISE.
MAC_verilog
- 以太网MAC网卡的Verilog源代码,可以节省TCP/IP协议的设计开发时间。-Verilog source code for Ethernet MAC network card, you can save the TCP/IP protocol design and development time.
UDP
- 利用verilog语言写的基于千兆网卡的UDP协议驱动-Use verilog language written based Gigabit Ethernet UDP protocol driver
ETH_GEN_CHK
- Ethernet packet generator and check (verilog),for Ethernet design purpose!
CH03_RGMII_UDP_TEST
- 基于RGMII的UDP网络数据通信,学习FPGA的千兆以太网通信(RGMII based UDP network data communication, learning FPGA Gigabit Ethernet communications)