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kenel_crypto
- 内核加解密算法 加解密函数库及其使用说明，详见附件。 find_cipher_by_name中参数ciphername可取的值为下面的组合，对应不同的模式: (des,des_ede3,aes,blowfish,cast5,dfc,idea,mars,rc5,rc6,serpent,twofish)-ecb (des,des_ede3,aes,blowfish,cast5,dfc,idea,mars,rc5,rc6,serpent,twofish)-cbc (des,des_ede3,aes,b
aes_core
- AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use,
aes
- AES Core Modules In this document I describe components designated to encoding and decoding using AES. aes enc — parametrizable component which can encrypt input data, using 128, 192 and 256 bit key, • aes dec — parametrizable component
aes_crypto_core_latest.tar
- Consecutive AES core Descr iption of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
AES
- AES算法的verilog代码，即AES算法IP核-ip core for AES
Rijndaeljava
- 用java语言实现了AES加密算法的核心算法RIJINDAEL。-Using java language to implement the AES encryption algorithm is the core algorithm RIJINDAEL.
aes_crypto_core_latest.tar_2
- VHDL CODE FOR AES CRYPTO CORE
aes
- AES的IP核,AES的加密解密算法，包括密钥扩展程序-aes core verilog
aes_core
- aes加密解密核,验证可用，可仿真，代码简洁，适合学习-aes core
xt_NFLOG
- core AES cipher using ARMv8 Crypto Extensions.
aes__code_based_on_verilog
- AES核心代码，用verilog写的，可供参考-aes core code using verilog for learning
AES
- The AES cipher core consists of a key expansion module, an initial permuta- tion module, a round permutation module and a final permutation module. The round permutation module will loop internally to perform 10 iteration (for 128 bit keys).
AES-File-EnDecryptor-Writed-by-CSharp-master
- 使用 C# 编写的AEC文件加密核心代码源码。(Use C# to write the AEC file encryption core code source code.)