搜索资源列表
aes-vhdl 使用vhdl语言实现aes（rijndael 算法）
- 使用vhdl语言实现aes（rijndael 算法），程序整体封装成为一个package，方便调用-Using vhdl language aes (rijndael algorithm), the program as a whole package as a package, easy call
crc.zip CRC校验程序
- CRC校验程序，使用了CRC-16和CRC-CCITT方法 ,CRC inspection program, which use crc-16 and crc-ccitt method
DES_Verilog
- 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test
80300di
- this a vhdl program for crc encoder and decoder-this is a vhdl program for crc encoder and decoder
use_3_shoft
- SHA-1的verilog程序，经过优化的了，希望可以对大家有帮助-SHA-1 of the verilog program, optimized, and hope that we can help you
tongxunjiekou
- 基于VHDL语言，实现串行通讯接口功能的主程序-The use of VHDL language implementation of the serial communication interface program
Multiplier
- 基于VHDL语言，实现串并乘法器设计主程序-Based on the VHDL language, to achieve the main program string and Multiplier Design
aes
- 其程序是用xilinx环境下编写的，风格是Verilog，请大家提意见。-The program is written using xilinx environment, style Verilog, please comments.
PCK_CRC3_D4
- CRC校验码生存程序 校验序列码生成多项式： X16+X13+X12+X11+X10+X8+X6+X5+X2+1 输入数据为16个字节（128位），输出16bit校验序列-CRC, the survival program check sequence code generator polynomial: X16+ X13+ X12+ X11+ X10+ X8+ X6+ X5+ X2+1 input data is 16 bytes (128 bits), output 16bit
mul
- 乘法器vhdl程序,主要是 修正后的乘法器，希望对大家有帮助-study the program of vhdl for multiplier
RSA-REPORT
- a simple VHDL program on RSA encryption technique
rbvt941
- 用VHDL编的一个实用自动打铃系统,EDA课设的一个经典题目源程序,-Use VHDL compiled a practical automatic ringing the bell system, EDA class of a classic topic source program,