搜索资源列表
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伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
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RC5/RC6 Base加密/解密源码 -RC5/RC6 Base encryption/decipher source code
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这是CRC字符串校验的源码，可对字符串校验后输出校验码-This is the CRC checksum of the source string can be output after the string checksum validation code
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内带3个sha1的C源码。经验证都可用。在我们项目中，已经用于验证SHA1的verilog-With three within the C source code sha1. Experience certificate are available. In our project, has been used to validate SHA1 of verilog
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3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
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用VHDL求rsa加密系统的密钥D（辗转相除法）-Using VHDL for rsa key encryption system D（Division algorithm）
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高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
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DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA
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AES加解密Verilog HDL源代码，具体的算法参照相关书籍，里面含有testbench-AES encryption and decryption Verilog HDL source code, reference books specific algorithm, which contains testbench
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使用verilog的128位aes加密源程序-Use verilog of 128 aes encryption source code
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verilog实现des的加密解密源代码-verilog realization of des encryption and decryption source code
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