搜索资源列表
Serial_fifo_function
- 该文件可以实现基于44b0的串口fifo功能-The document can be achieved 44b0-based features of the serial fifo
EZUSB_Bulk
- USB_BLUK例程，BLUK传输模式，是配合cypress公司EZ_USB FX2系列芯片的源码-USB_BLUK routine, BLUK transmission mode, is in line with cypress company EZ_USB FX2 series chips source
UART16550
- UART控制器，集成FIFO，寄存器，数据位宽8位-UART controller, with FIFO, register, databus 8bits
fifodesign
- 同步fifo设计，与原来上传的异步fifo不同。同步fifo是使用同一个时钟，异步fifo使用不同的时钟域-synchronize fifo design
GPIF_FIFO_Transactions_Auto_mode
- USB的GPIF中FIFO传输方式的例子-keyword: cypress USB GPIF fifo
seriafifo
- LPC2124，串口FIFO，接收功能实验，触点不同，效果有区别，实验为证-LPC2124 UART FIFI example
16550u
- Dos下使用串口实现先进先出,支持COM1-COM4- 16550 is a shareware program designed to allow the unlocking of the internal fifo buffer present in the UART chip of the same name. The program will scan all four COM ports (COM1:- COM4
51FIFO
- 51FIFO,串口缓存收发。很有借鉴意义-51FIFO, send and receive serial buffer. Useful reference
FIFO_architecture_of_FX2LP
- cypress 68013A USB2.0开发 中FIFO架构的介绍，以及相关register的说明-cypress 68013A USB2.0 design FIFO_architecture
37105319GPIF_fifo
- ezusb芯片的应用。主要是68013的fifo功能的介绍，开发usb2.0项目有很大的帮助-ezusb chip applications. 68013 fifo function is mainly the introduction and development projects of great help to usb2.0
fifo_iso_read
- 基于68013芯片的FIFO自动输入同步传输，有固件和上位机程序-68013 chip FIFO automatically based on input synchronous transmission, with firmware and PC application
51_uart_fifo51
- 51_uart_fifo51 串口收发程序源代码 环形缓冲区实现-Serial transceivers to achieve ring buffer source code
mmtwo
- 用matlab实现 mm2 队列模型的系统仿真基于先进先出的时间连续模型-Mm2 queue system simulation model based on continuous model of the FIFO using matlab
Apptest
- USB2.0 接收FIFO数据，下位机是CYC68013-USB 2.0 receive FIFO data
tongbufifo
- 一个简单的同步fifo，可以帮助需要的朋友-A simple synchronous fifo, can help a friend in need
FIFO_IN
- EZ-USB简单实现Slave FIFO工作模式。供初学入门~-EZ-USB is simple to achieve the Slave FIFO work mode. For beginner entry to
fifo2
- 一种简单的FIFO的verilog代码，有利于理解FIFO的工作原理-code of fifo in verilog
trans_and_delete
- 1/2,3/4可配置的卷积码编码，其中需要用要FIFO的IP核-1/2, 3/4 convolutional code encoder can be configured with a FIFO wherein IP core
CummingsSNUG2002SJ_FIFO1_rev1_1
- FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1
firmware
- slave fifo 的固件程序完整版希望对大家有帮助-slave fifo firmware completed