搜索资源列表
freq_conv
- 利用fifo实现频率域卷积的接口控制,主要体现在fifo的接口控制功能-Achieve frequency domain convolution using the fifo interface control, mainly in the fifo interface control functions
uartfifo
- 将产生的数据存入FIFO中并由串口发送出去。-The resulting data into the FIFO by the serial port to send out.
SCIFIFOINTtext2
- 本程序是上位机与DSP通讯，DSP以FIFO的接收中断方式接收上位机的数据，再将数据发回给上位机-This procedure is the communication between PC and DSP, DSP receiver FIFO interrupt to the host computer receives the data, then the data is sent back to the host computer
xfft_v3_2_pipe_64
- vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband-vhdl ifft and fifo code with xilinx ip core to implement OFDM Basisband
SLAVE-FIFO-16BITS
- CY7C68013a的slavefifo的固件源代码，keil编写，以及使用FPGA向EP6端点写数据的verilog源代码，没有错误，可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you can compile successfully!
spi_cbb
- 基于FPGA设计，verilog语言变成的，SPI通用接口模块，顶层已封装成类似标准的FIFO接口；提供仿真文件；仿真器为modelsim10.0c，波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard
gpif_to_extfifo-fifo-rw
- USB GPIF 接口编程源码，经过验证-The source code for USB GPIF. It was verifed.
uart
- 黑金FPGA开发板串口收发程序，其中加入FIFO模块作为输入输出缓冲-Black gold development board FPGA procedures, which joined the FIFO module as input and output buffer
FirmWare
- CY7C68013 USB2.0传输 在SLAVE FIFO模式下的 C固件-CY7C68013 USB2.0 transfer，in the mode of SLAVE FIFO
generic_fifos_latest.tar
- FIFO通用，可以尝试一下，很实用的IP核-FIFO generic
uartfifo
- fifo模式下的uart串口verilog的源程序-fifo mode serial uart verilog source
USB
- USB芯片 的驱动程序，实现FT22332H的异步FIFO模式的数据传输。-USB chip drivers, data transmission FT22332H asynchronous FIFO mode.
CYUSB3014 Example Code
- Slave fifo 4 flags example
UART
- UART文件 包括发送器 接收器 fifo 测试文件-UART file includes a receiver transmitter fifo test files
UART_FIFO
- FPGA，串口调试程序，接收模块，含FIFO IP核-FPGA uFF0C u4E32 u53E3 u8C03 u8BD5 u7A0B u5E8F uFF0C u63A5 u6536 u6A21 u5757 uFF0C u542BFIFO IP u6838
心率 (1)
- 读取FIFO数据，装换成实际的数值，进度未加算法(Read the FIFO data and numerical into actual progress, without algorithm)
13_usb_test
- READ 16BIT DATA FROM EP2 FIFO AND SEND TO EP6 FIFO
43411050
- 这个是UART的控制器,已经跑通过,分4个模块,波特率生成,发送,接收和fifo,可供初学者参考()
tx_interface_project
- 带FIFO的串口发送模块，简单的FPGA串口发送模块(Serial transmission module with FIFO)