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sp
- 分频和串并变换在一个process中，可以运行-Divider and series, and transform in a process, you can run the
9600divider
- 任意分频器,可以实现FPGA的CLK分频功能，已通过编译-Arbitrary frequency divider can be achieved FPGA-CLK sub-band capabilities, has passed the compilation
dividerwithsignal
- 本程序是用verilog实现带符号的二进制除法器。本代码可用。-to realize the divider
shiyanbaogao
- 了解ISE平台的基本环境，编译程序，在MC8051 IP核中，要求实现：增加PLL锁相环，扩大内部RAM，定时器，串口和外部中断等资源，并增加乘法器和除法器的功能。-ISE platform to understand the basic environment, compiler, the MC8051 IP core, the requirement to achieve: increased PLL phase-locked loop, expanding the internal RAM
Power-splitter
- ADS（Advanced Design System）软件设计微带功率分配器-ADS (Advanced Design System) software design microstrip power divider
ISE-graphics
- 3D图形，单精度浮点乘法器，单精度浮点除法器，单精度浮点乘累加器-3D graphics,single float pointing multiplier, single float pointing divider,single float pointing MAC
8253
- 微机实验 1、编写程序：使用8253的计数器0和计数器1实现对输入时钟频率的两级分频，得到一个周期为1秒的方波，用此方波控制蜂鸣器，发出报警信号，也可以将输入脚接到逻辑笔上来检验程序是否正确。 2、使用8253，编写一个时钟程序。 -Microcomputer Experiment 1, the preparation process: 8253 counter 0 and counter two of the input clock frequency divider, a per
clk_div3
- 自己用xilinx ise编写的分频器程序，可以奇分频偶分频，分频系数可以自己设置。方便产生各种时钟信号-Divider program prepared using the Xilinx ISE, odd even divide divider division factor can set up their own. And convenient produce a variety of clock signal
fenpinqi
- 数字分频器，包括分频器单位冲击响应及幅频响应-Digital frequency divider, including frequency divider unit impulse response and amplitude frequency response
devider10
- 实现对时钟信号的二分频和十分频，二者作为系统的两个输出(Realization of two frequency division and ten frequency division of clock signal,and the two are used as the two output of the system.)