搜索资源列表
Autostart
- 该工具用于使用MAXII CPLD实现了Target I2C功能,例程很全,包括Modelsim仿真
ctc
- 上传的是WIMAX系统中，CTC译码算法的仿真程序，基于Modelsim
PcodeGeneration
- 在ModelSim或其他支持Verilog语言编译的环境中仿真可得GPS的P码及与卫星数据码调制后的波形，其中一个为源程序，另一个为测试程序-ModelSim or other support in the language Verilog simulation environment to compile available GPS P-code and code of satellite data after the modulation waveform, one for the sour
ca_code_gen
- CA_Code_Generator.vhd用于生成GPS的32颗卫星的CA码程序，经过测试验证并消除了毛刺；CA_TEST_BENCH.vhd内带测试程序，直接可调用MODELSIM进行测试验证，留有用户接口，方便用户产生其他卫星的CA码。-CA_Code_Generator.vhd used to generate the 32 GPS satellites CA code program, tested and verified to eliminate the burr CA_TEST_
uartnew
- 好用的UART通信源码，使用Verilog 编写 在QUARTUS下完成，并用ModelSim仿真通过-Source-to-use UART communications, the use of Verilog in Quartus to complete the preparation and use of ModelSim simulation through
GPS_CA_Generator_vhdl
- GPS对应的CA短码发生电路的VHDL描述程序，附带modelsim仿真用源文件-GPS code corresponding to happen CA short circuit VHDL descr iption of the procedure, with ModelSim simulation using the source file
QAM_vhdl_modelsim
- qam的vhdl程序，包含载波恢复等。同时含有modelsim仿真文件，希望有所帮助-qam vhdl modelsim
modlesimcrack
- altera配套modelsim破解程序，绝对好用！注意要改环境变量-altera crack modelsim matching procedure, the absolute ease of use! Attention to environment variables to be changed
Modelsim
- MODELSIM,YIANGJIAN仿真软件-SDDD
ModelSim-
- 此资料为modelsim使用教程6.0，包括初学者全套中文资料，为初学者提供很大帮组。-This information is modelsim tutorial 6.0, including a full set of Chinese information for beginners, providing great help group for the beginner.
key_filter
- 用于FPGA的按键消抖的Verilog文件，经过modelsim仿真和下板验证。-Verilog file for FPGA key debounce, after modelsim simulation and verification under the plate.
uart
- uart串口通信协议 可以在modelsim里进行仿真验证- uart can be simulation in modelsim
FM
- MATLAB仿真 FM调制和解调过程，并把解调出来的数据写入文本，方便quartus和modelsim仿真调用(MATLAB simulation FM modulation and demodulation process, and the data written into the text of the demodulation, to facilitate the quartus and Modelsim simulation calls)
BtoC
- 文件中有两种方法实现并串转换模块代码的编写，可以在modelsim软件中正确仿真(There are two methods in the file to achieve the serial conversion module code writing, can be correctly simulated in Modelsim software)
adder_test
- 使用modelsim软件编写半加法器和4位加法器，(Using Modelsim software to write a half adder and a 4 bit adder,)
fpga_slavefifo2b_verilog
- fpga控制USB接口数据收发，包含verilog 仿真代码和调试工程(fpga control usb3.0, modelsim simulation, verilog language)