采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.

状态机，串口收发，以及奇偶校验。 even_parity.v奇偶校验； receive_byte.v字节接收； send_byte.v字节发送(state machine,UART even_parity.v even parity; receive_byte.v receiving byte; send_byte.v sending byte)