搜索资源列表
fskpsk
- FSK和PSK的ewb实现，很好很强大的调制系统。-Ewb of FSK and PSK to achieve good modulation system is very powerful.
yuyintongxin
- 基于CPLD的语音通信系统设计与实现毕业设计 原版包括程序源码，各部分仿真图，框图-CPLD-based voice communications system design and implementation of the design of the original graduate program, including source code, the part of simulation diagram, block diagram
verilogHDL
- RS（31，15）译码关键步骤的veilog HDL算法实现，包括关键方程求解，错误位置估计，错误值计算等-RS (31,15) decoding a key step in the algorithm veilog HDL, including key equations, position estimation error, error value, such as
11912885serial
- 简单描述了rs232 与pc的通信，采用vhdl硬件描述语言实现，调试通过-A brief descr iption of the rs232 communication with pc
floatingfoint
- this a descr iption for the floating point for the WIMAX-this is a descr iption for the floating point for the WIMAX
urn_nbn_se_liu_diva-6949-1__fulltext
- Viterbi decoder algorithm
Alu1232
- An 8-bit ALU with 16 operations: logic, arithmetic, shifts.
Receiver
- This file recieves the serial data from the UART and forward to Serial To Parallel module
turtorial1
- matlab code for digital up conversion filter and the comand to generate the corresponding vhdl
fangzhen
- 卷积码和循环码的verilog编码以及仿真结果图，-Convolutional codes and cyclic codes and the coding verilog simulation results map
0s
- this the vhdl code for ladpc decoder-this is the vhdl code for ladpc decoder
pll
- 一个实现任意倍频的，输入参考频率未知的pll，已综合实现-frequency multiple rely on dpll，unknown reference input clock
sdcard_mass_storage_controller
- A host controlled ot control sd cards
src
- DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output. -DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output.
usb_phy_verilog.tar
- usb的逻辑设计代码，供大家研究或使用，参考-the logic design usb code, or use for your research, reference
i2c
- i2c 一个基于 对 EEPROM 读写数据的数据接口-i2c interface
usb_funct
- usb 2.1 IP 的 东西 很好的 是 我的 -usb2.1 IP it s so eay to me to you
clock
- 由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
FPGAjianpansaomiao
- FPGA的键盘扫描程序，VHDL编程，大家下载看吧。-FPGA keyboard scanner, VHDL programming